comp.lang.vhdl

Date Index

Unknown fault: signals not assigning, Trit
- Re: Unknown fault: signals not assigning, KJ
  - Re: Unknown fault: signals not assigning, Trit
Search arithmetic library, Yannick
- Re: Search arithmetic library, Tricky
ISE 10.1 and Timing Simulation Errors, john
- Re: ISE 10.1 and Timing Simulation Errors, Brian Drummond
- Re: ISE 10.1 and Timing Simulation Errors, Tricky
  - Re: ISE 10.1 and Timing Simulation Errors, john
    - Re: ISE 10.1 and Timing Simulation Errors, Tricky
    - Re: ISE 10.1 and Timing Simulation Errors, john
    - Re: ISE 10.1 and Timing Simulation Errors, Tricky
    - Re: ISE 10.1 and Timing Simulation Errors, john
    - Re: ISE 10.1 and Timing Simulation Errors, Tricky
use alias in port declaration?, Mike Dearman
- Re: use alias in port declaration?, KJ
  - Re: use alias in port declaration?, Mike Dearman
VHDL help., devil6600
- Re: VHDL help., Enes Erdin
  - Re: VHDL help., Enes Erdin
- Re: VHDL help., Tricky
  - Re: VHDL help., Tricky
any way to avoid warnings about unused outputs in XST?, Ken Cecka
- Re: any way to avoid warnings about unused outputs in XST?, Mike Treseler
  - Re: any way to avoid warnings about unused outputs in XST?, Ken Cecka
    - Re: any way to avoid warnings about unused outputs in XST?, Ken Cecka
    - Re: any way to avoid warnings about unused outputs in XST?, Mike Treseler
    - Re: any way to avoid warnings about unused outputs in XST?, Mike Treseler
    - Re: any way to avoid warnings about unused outputs in XST?, Ken Cecka
Test bench, john
- Re: Test bench, Mike Treseler
- Re: Test bench, KJ
ERROR: infix expression "<=" with simple vectors, Trit
- Re: ERROR: infix expression "<=" with simple vectors, nuckols . jeff
  - Re: ERROR: infix expression "<=" with simple vectors, nuckols . jeff
    - Re: ERROR: infix expression "<=" with simple vectors, Trit
    - Re: ERROR: infix expression "<=" with simple vectors, Tricky
    - Re: ERROR: infix expression "<=" with simple vectors, Trit
    - Re: ERROR: infix expression "<=" with simple vectors, Andy Peters
    - Re: ERROR: infix expression "<=" with simple vectors, Trit
    - Re: ERROR: infix expression "<=" with simple vectors, Jim Lewis
  - Re: ERROR: infix expression "<=" with simple vectors, Trit
    - Re: ERROR: infix expression "<=" with simple vectors, Jim Lewis
Variable array size in entity, FabM
- Re: Variable array size in entity, Enes Erdin
- Re: Variable array size in entity, Tricky
  - Re: Variable array size in entity, FabM
  - Re: Variable array size in entity, Jim Lewis
After Place and Route, RealInfo
- Re: After Place and Route, goouse
  - Re: After Place and Route, RealInfo
- Re: After Place and Route, Alan Fitch
help me, aralimaradsir
- Re: help me, Tricky
- Re: help me, goouse
need vhdl code, kasthuri . m92
- Re: need vhdl code, kennheinrich
- Re: need vhdl code, Tricky
  - Re: need vhdl code, Jacko
Compile time, gervaz
- Re: Compile time, Alex
  - Re: Compile time, mattia
A "lurker thankyou" -was [Re: vhdl syntax query], Richard Owlett
- Re: A "lurker thankyou" -was [Re: vhdl syntax query], Martin Thompson
Help with creating a very small CPU, TweedleDee
- Re: Help with creating a very small CPU, kennheinrich
  - Re: Help with creating a very small CPU, kennheinrich
    - Re: Help with creating a very small CPU, TweedleDee
  - Re: Help with creating a very small CPU, Mike Treseler
- Re: Help with creating a very small CPU, Pieter Hulshoff
- Re: Help with creating a very small CPU, jacko
Random Value for LFSR (just simulation), Martin
- Re: Random Value for LFSR (just simulation), Tricky
  - Re: Random Value for LFSR (just simulation), kennheinrich
    - Re: Random Value for LFSR (just simulation), Brian Drummond
- Re: Random Value for LFSR (just simulation), Marcus Harnisch
- Re: Random Value for LFSR (just simulation), whygee
- Re: Random Value for LFSR (just simulation), David Binnie
one hot machine without elsif, Brad Smallridge
- Message not available
  - Re: one hot machine without elsif, jtw
    - Re: one hot machine without elsif, goouse
- Re: one hot machine without elsif, goouse
  - Re: one hot machine without elsif, Tricky
    - Re: one hot machine without elsif, Brad Smallridge
    - Re: one hot machine without elsif, Mike Treseler
    - Re: one hot machine without elsif, Brad Smallridge
    - Re: one hot machine without elsif, KJ
  - Re: one hot machine without elsif, Jim Lewis
- Re: one hot machine without elsif, Jim Lewis
  - Re: one hot machine without elsif, Brad Smallridge
    - Re: one hot machine without elsif, Jim Lewis
Using a memory initialization file, Walther
- Re: Using a memory initialization file, Aiken
- Re: Using a memory initialization file, Mike Treseler
  - Re: Using a memory initialization file, Walther
    - Re: Using a memory initialization file, Tricky
    - Re: Using a memory initialization file, PlayDough
    - Re: Using a memory initialization file, Amal
    - Re: Using a memory initialization file, Walther
    - Re: Using a memory initialization file, Alan Fitch
- Re: Using a memory initialization file, Barry
Shift registers, gervaz
- Re: Shift registers, Tricky
arrrrg!, Ken Cecka
- Re: arrrrg!, kennheinrich
- Re: arrrrg!, Al Muliman
  - Re: arrrrg!, Al Muliman
    - Re: arrrrg!, Al Muliman
    - Re: arrrrg!, Nicolas Matringe
    - Re: arrrrg!, Al Muliman
    - Re: arrrrg!, Brian Drummond
    - Re: arrrrg!, Al Muliman
    - Re: arrrrg!, Ken Cecka
    - Re: arrrrg!, Brian Drummond
    - Re: arrrrg!, Al Muliman
    - Re: arrrrg!, Al Muliman
- Re: arrrrg!, Dave Higton
  - Re: arrrrg!, Ken Cecka
    - Re: arrrrg!, Dave Higton
    - Re: arrrrg!, Ken Cecka
    - Re: arrrrg!, Brian Drummond
    - Re: arrrrg!, Alan Fitch
    - Re: arrrrg!, Brian Drummond
Multiple instances, mattia
- Re: Multiple instances, KJ
  - Re: Multiple instances, mattia
    - Re: Multiple instances, KJ
    - Re: Multiple instances, mattia
Reading an Array of vectors., Niv (KP)
- Re: Reading an Array of vectors., Ken Cecka
  - Re: Reading an Array of vectors., Ken Cecka
  - Re: Reading an Array of vectors., Jim Lewis
    - Re: Reading an Array of vectors., Andy
- Re: Reading an Array of vectors., Alan Fitch
  - Re: Reading an Array of vectors., Alan Fitch
    - Re: Reading an Array of vectors., Jonathan Bromley
    - Re: Reading an Array of vectors., Niv (KP)
    - Re: Reading an Array of vectors., Niv (KP)
    - Re: Reading an Array of vectors., Jonathan Bromley
    - Re: Reading an Array of vectors., Andy
    - Re: Reading an Array of vectors., Jonathan Bromley
    - Re: Reading an Array of vectors., Andy
    - Re: Reading an Array of vectors., Andy
    - Re: Reading an Array of vectors., Jonathan Bromley
    - Re: Reading an Array of vectors., Jonathan Bromley
    - Re: Reading an Array of vectors., Andy
    - Re: Reading an Array of vectors., kennheinrich
    - Re: Reading an Array of vectors., Jonathan Bromley
    - Re: Reading an Array of vectors., Alan Fitch
unsigned(), unsigned'(), to_unsigned(), Shannon
- Re: unsigned(), unsigned'(), to_unsigned(), Tim McBrayer
  - Re: unsigned(), unsigned'(), to_unsigned(), Mike Treseler
    - Re: unsigned(), unsigned'(), to_unsigned(), Jim Lewis
    - Re: unsigned(), unsigned'(), to_unsigned(), Mike Treseler
    - Re: unsigned(), unsigned'(), to_unsigned(), Shannon
    - Re: unsigned(), unsigned'(), to_unsigned(), Brian Drummond
4 digit input number, My Name
- Re: 4 digit input number, Tricky
learning vhdl - state machines, Al Muliman
- Re: learning vhdl - state machines, Jonathan Bromley
  - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Jonathan Bromley
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Andy
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Andy
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Martin Thompson
    - Re: learning vhdl - state machines, Al Muliman
- Re: learning vhdl - state machines, Mike Treseler
  - Re: learning vhdl - state machines, Jonathan Bromley
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Martin Thompson
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, Al Muliman
    - Re: learning vhdl - state machines, beky4kr
    - Re: learning vhdl - state machines, Mike Treseler
division of two 4-bit vectors, My Name
- Re: division of two 4-bit vectors, Rob Gaddi
  - Re: division of two 4-bit vectors, My Name
- Re: division of two 4-bit vectors, Jonathan Bromley
  - Re: division of two 4-bit vectors, kennheinrich
    - Re: division of two 4-bit vectors, Jonathan Bromley
    - Re: division of two 4-bit vectors, My Name
    - Re: division of two 4-bit vectors, kennheinrich
    - Re: division of two 4-bit vectors, Aiken
    - Re: division of two 4-bit vectors, My Name
    - Re: division of two 4-bit vectors, Dave
  - Re: division of two 4-bit vectors, Benjamin Couillard
    - Re: division of two 4-bit vectors, Benjamin Couillard
    - Re: division of two 4-bit vectors, Andy
ISE 10.1, john
- Re: ISE 10.1, Alan Fitch
  - Re: ISE 10.1, john
    - Re: ISE 10.1, Alan Fitch
    - Re: ISE 10.1, john
    - Re: ISE 10.1, Alan Fitch
    - Re: ISE 10.1, john
    - Re: ISE 10.1, Alan Fitch
    - Re: ISE 10.1, john
Bit reversing, Mad I.D.
- Re: Bit reversing, Ken Cecka
- Re: Bit reversing, Jim Lewis
  - Re: Bit reversing, Jonathan Bromley
XC3S1000-4FT256, john
- Re: XC3S1000-4FT256, Pascal Peyremorte
Is this phase-accumulator trick well-known???, Jonathan Bromley
- Re: Is this phase-accumulator trick well-known???, Mike Treseler
  - Re: Is this phase-accumulator trick well-known???, Jonathan Bromley
FIR ADDER IMPLEMENTATION, RealInfo
- Re: FIR ADDER IMPLEMENTATION, Jonathan Bromley
- Re: FIR ADDER IMPLEMENTATION, Barry
  - Re: FIR ADDER IMPLEMENTATION, kennheinrich
clk synchronization of reset signal, axr0284
- Re: clk synchronization of reset signal, Rob Gaddi
- Re: clk synchronization of reset signal, Aiken
Draft paper submission deadline extended: HPCNCS-09, sr
clock generation by divide and reset, J.Ram
- Re: clock generation by divide and reset, Enes Erdin
  - Re: clock generation by divide and reset, perich
Embedded System Call For Papers 2009, My Name
Testbench Question: Internal signals., BLF
- Re: Testbench Question: Internal signals., ALuPin@xxxxxx
  - Re: Testbench Question: Internal signals., JM
- Re: Testbench Question: Internal signals., Mike Treseler
  - Re: Testbench Question: Internal signals., BLF
    - Re: Testbench Question: Internal signals., BLF
Re: Hello, quick question, Symon
help in VHDL procedure programming, VIPS
- Re: help in VHDL procedure programming, Enes Erdin
- Re: help in VHDL procedure programming, Mike Treseler
synthesis question of fixed point library, sanborne
- Re: synthesis question of fixed point library, KJ
Which Verification Methodologies Are You Using?, harrytheasicguy
- Re: Which Verification Methodologies Are You Using?, Nicholas Paul Collin Gloucester
Test vector for only MSB being set., Niv (KP)
- Re: Test vector for only MSB being set., Tricky
- Re: Test vector for only MSB being set., Jonathan Bromley
  - Re: Test vector for only MSB being set., Niv (KP)
face recognition using neural networks, Rash
- Re: face recognition using neural networks, Tricky
Automating VHDL Simulations in ModelSim, Georg
- Re: Automating VHDL Simulations in ModelSim, HT-Lab
  - Re: Automating VHDL Simulations in ModelSim, Georg
    - Re: Automating VHDL Simulations in ModelSim, Mike Treseler
    - Re: Automating VHDL Simulations in ModelSim, Georg
    - Re: Automating VHDL Simulations in ModelSim, Tricky
    - Re: Automating VHDL Simulations in ModelSim, Georg
    - Re: Automating VHDL Simulations in ModelSim, Tricky
    - Re: Automating VHDL Simulations in ModelSim, Georg
    - Re: Automating VHDL Simulations in ModelSim, petrovski101
    - Re: Automating VHDL Simulations in ModelSim, Jan Decaluwe
    - Re: Automating VHDL Simulations in ModelSim, petrovski101
    - Re: Automating VHDL Simulations in ModelSim, Jeff Cunningham
    - Re: Automating VHDL Simulations in ModelSim, HT-Lab
- Re: Automating VHDL Simulations in ModelSim, Jim Lewis
- Re: Automating VHDL Simulations in ModelSim, Jonathan Bromley
  - Re: Automating VHDL Simulations in ModelSim, Georg
different between !=0 and >0 in the net list level, Aiken
- Re: different between !=0 and >0 in the net list level, Tricky
  - Re: different between !=0 and >0 in the net list level, Andy
Re: vhdl questions from a verilog person, Tricky
Re: "when others" question, Peter
Re: superposition of a square wave over a sine wave, Chris Maryan
FIR Coefficients, RealInfo
- Re: FIR Coefficients, kennheinrich
  - Re: FIR Coefficients, RealInfo
Re: vhdl code, Rash
- Re: vhdl code, kennheinrich
- <Possible follow-ups>
- vhdl code, Rash
- vhdl code, Rash
Spartan 3A Starter Kit Comm Problem, TTX
Call For Papers: WORLDCOMP'09 (computer science, computer engineering, and applied computing conferences), July 13-16 2009, USA, A. M. G. Solo