Re: VHDL-2008




"Kim Enkovaara" <kim.enkovaara@xxxxxx> wrote in message
news:OXBHk.77838$_03.1118@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
HT-Lab wrote:

As you mentioned we *all* need to speak to our vendors/distributors to
get this standard adopted as quick as possible. The process is simple,
send them an email asking for an Enhancement Request (ER) to get this
standard implemented.

The more realistic way to get features implemented is to ask smaller
features which are really needed.

I agree, hence I wrote "better" between brackets.

Asking for the whole standard will
make the enhancement very big task, and when the work amount is big
and priority is low it won't get implemented.

Perhaps, however, from a marketing point of view it makes very little sense
to implement just one feature. What they want is to be able to say, we
support VHDL-2008 standard, which is slighly better than saying we support
only case? from the VHDL2008 standard :-)


It took years to get the SystemVerilog completely implemented to the
simulators.

This is a silly comparison, have you ever seen the SystemVerilog LRM? it is
absolutely massive and it dwarfs the VHDL-2008 enhancements. If you look at
Modelsim most (if not all) of the enhancements are already available in one
way or another. The only problem for companies like Mentor is that they need
to implement the standard across a number of products (Modelsim, Precision,
HDL Designer) and I suspect this is going to take time.

I have already asked Mentor several times to look at this standard,
unfortunately according to a Mentor engineer I am one of the few who has
done this,

They already have some preliminary support. Read the
docs/technotes/vhdl200x.note

Have you? I checked it out when it first became available and was highly
disappointed. The enhancements are nothing more than supporting the
fixed/floating point package (without any waveform support!) and a simple
VHDL package for the Verilog $finish task.

Hans
www.ht-lab.com



--Kim


.



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