Re: Mixed clocked/combinatorial coding styles

On Aug 21, 2:01 am, Kim Enkovaara <kim.enkova...@xxxxxx> wrote:
rickman wrote:
On Aug 20, 9:45 am, KJ <kkjenni...@xxxxxxxxxxxxx> wrote:
On Aug 18, 5:23 pm, rickman <gnu...@xxxxxxxxx> wrote:

If you don't use async resets, then you don't use FPGAs, at least none
that I am aware of. FPGAs have a global set/reset signal that
initializes the FFs on power up. You don't have to drive it with your

Of course with FPGAs also initial values can be used and then no reset
is connected to the FF. The initial value comes from the configuration
file in that case.

But this requires the global set reset signal. That is how the FFs
get their initial state.

own signal, but it is active regardless of your code. But if you want
to control the state of the FF on power up, then you need to use a
register template with an async reset.

Not always. You can also use the FFs without any reset and give initial
values for the signals. Most synthesizers can transfer those values
to configuration image.

I don't think this is the rule. If you want to write portable code,
you need to use a reset as part of the clocked process.


The shift register you describe driving a synchronous reset is what I
use, except I use it to drive the async reset. Since the output of
the shift register is sync'd to the clock, it will not cause
problems. It also does not use any extra resources since it will be
mapped to the dedicated GSR signal in the FPGA.

It might cause problems, because the internal global reset lines inside
FPGA are quite slow. And the signal might not propagate trough the FPGA
during one clock cycle. I have seen problems with this kind of reset
style, the design locked once every 100 startups. The cause was that on
some one-hot statemachines the FFs got reset deasserted on different
clock cycles, and there was no guard logic in the state machines to get
out from that situation.

Maybe if you are running at 200 MHz. There are always speed issues in
any design. That is why you use timing constraints. You do use
timing constraints, right?

Rick
.

Relevant Pages

  • Re: Need for reset in FPGAs
    ... usually a reset signal is applied to put the FFs of an FPGA into a known ... The FFs always come up in a guaranteed way after power-up - the ... bitstream you feed into the FPGA defines their power-up state. ...
    (comp.arch.fpga)
  • Re: The FFs with synchronous reset perform worse?
    ... The FFs can be reset synchronously or asynchronously. ... reset flops were not larger in area than non-reset flops from which ... and what you say is about ASIC or FPGA? ...
    (comp.arch.fpga)
  • Re: Need for reset in FPGAs
    ... usually a reset signal is applied to put the FFs of an FPGA into a known ... logic/state machines into complete disarray. ...
    (comp.arch.fpga)
  • Re: spartan 3an application
    ... When this signals is one, you count up and if it's 0 you count down. ... RESET, //input button ... reg Qreset; ... wire PULSE_NEW_out; ...
    (comp.lang.verilog)
  • Re: Mixed clocked/combinatorial coding styles
    ... I wouldn't use a device input that performs a device wide reset ... as a clock input had better be able to cope with the clock shutting ... The outputs of the shift registers become the reset signals ... requirement to go active at the end of configuration, ...
    (comp.lang.vhdl)
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