Re: Nibz processor @ 472 LEs (16 bit generic specified)

On 12 Aug, 12:50, KJ <kkjenni...@xxxxxxxxxxxxx> wrote:
On Aug 12, 6:07 am, "Symon" <symon_bre...@xxxxxxxxxxx> wrote:



"KJ" <kkjenni...@xxxxxxxxxxxxx> wrote in message

news:bwmnk.32987$co7.7807@xxxxxxxxxxxxxxxxxxxxxxx

I'll strongly second Mike's advice and I'd go further and state that
latches are never safe unless
- The device actually has a hardware latch as a resource (unlikely
now-a-daze)
- The synthesized code ends up mapping the source code to the above
mentioned latch
- The latch enable signal is sourced from a flip flop.

KJ

Hi Kevin,

All the Xilinx FPGAs I use have latches built in.

Then that meets the first requirement. Making sure that your code
gets mapped to those elements to meet #2 is still a manual
verification task. As long as one doesn't get too creative in
applying logic to generating the latch enable/gate signal then it
should all work out.

Also, I
think your third requirement is awry if by 'latch enable' you mean what I
would call the 'gate'. Normally my latched designs have the gate fed from a
clock.

Right, I should've said something more along the lines of that the
latch enable/gate signal must have absolutely no glitches, (i.e. like
a clock)...the point being that the output of any logic function
should not be used...amazingly enough, that simple point was the cause
for several failures that I investigated. The other common failure
being when the device didn't have hard latches so they got cobbled
together out of the existing logic but didn't cover the logic hazard
(or race condition if you prefer) either explicitly or because it got
optimized away since it's redundant...all of that was a long while ago
though.

KJ

Ya not the problem now, got rid of all inferred latches, added carry
register bit, now at 33+ MHz. Still one fault to fix, and zero
assignments to do on unused state machine states. Very compact now,
but leaves instruction register in q register on a call instruction,
so must fix this.

I assume Quartus means synchronous registered latches, when it says
latches. Clocked latches would be another way of saying this.

cheers
jacko
.

Relevant Pages

  • Re: Inferred latches questions
    ... Latches are transparent. ... The data input of a latch must not change short before the latch is disabled. ... -- variable to hold the sum a + b when determinig overflow variable tmp: ... In an ALU it may be a good idea, to store flags, like the overflow flag. ...
    (comp.lang.vhdl)
  • Re: Nibz processor @ 472 LEs (16 bit generic specified)
    ... The device actually has a hardware latch as a resource (unlikely ... The synthesized code ends up mapping the source code to the above ... All the Xilinx FPGAs I use have latches built in. ... The other common failure ...
    (comp.lang.vhdl)
  • Latches: What Are They For?
    ... I'm just starting to get into embedded systems and I recently stumbled across latches. ... It is my understanding that I'd usually set the bits (in my case, seven bits for a 7-segment LED display) on my microcontroller first, and then set the input enable bit high on the latch. ... At some point, I'd imagine that I'd have to set both the "input enable" and "output enable" pins back to low; but, I'm not sure exactly when to do this. ...
    (comp.arch.embedded)
  • Re: Cant latch top.
    ... I couldn't get the latches to latch. ... Wind the windows down or open the doors first ... but the windows were open. ...
    (rec.autos.makers.mazda.miata)
  • Re: Cant latch top.
    ... I couldn't get the latches to latch. ... I tried adjusting them (turning the adjusting ... nut to extend the latches as far as possible, ...
    (rec.autos.makers.mazda.miata)
Loading