Re: VHDL Operator associativity (Quartus II parser bug?)
- From: Jonathan Bromley <jonathan.bromley@xxxxxxxxxxxxx>
- Date: Thu, 19 Jun 2008 17:39:35 +0100
On Thu, 19 Jun 2008 09:23:18 -0700 (PDT), Fons wrote:
This is confusing, I'm not following the book but the LRM, and it
states that or and and have the same precedence.
Yes, but LRM 7.1 (Expressions) gives the BNF for expressions,
and there you can clearly see that it is not possible to
combine more than one kind of logic operator in the same
expression unless you use parentheses, which can turn an
"expression" into a "primary". The same BNF also ingeniously
prohibits the use of more than one "nand" or "nor" operator
in an expression without parentheses, while allowing such
things as
a and b and c
So the folk who told you that "and" and "or" have different
precedence are indeed wrong, but it doesn't matter a scrap
because you can never use them together in an un-parenthesised
expression.
Why, by the way, are you so keen to strip unwanted parentheses?
Parentheses are good, especially in machine-generated code,
and are completely free after the compiler has done its work.
They do a good job of sparing us from our own idiocy.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
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