Re: How to "or" a generic array of std_logic_vector ?
- From: KJ <kkjennings@xxxxxxxxxxxxx>
- Date: Mon, 9 Jun 2008 12:40:20 -0700 (PDT)
On Jun 9, 2:07 pm, Andy <jonesa...@xxxxxxxxxxx> wrote:
On Jun 8, 6:52 pm, "KJ" <kkjenni...@xxxxxxxxxxxxx> wrote:
<HansWernerMarsc...@xxxxxx> wrote in message
news:1fdcc58c-906c-4ec7-ad33-c9de3f635e34@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
I want to "or" the "bits" of std_logic_vector for each element of the
vector like this.
data_out(i) shall be '1' if one of the elements of the vector has set
this bit to one.
Somewhat similar to the process approach already covered in this thread is
to use a generate statement...basically the same amount of typing and debug
Gen_This : for i in data_out'range generate
data_out(i) <= '1' when unsigned(data_out_array(i)) /= 0;
end generate Gen_This;
KJ
The problem (latches) with this solution as well as that in the OP is
that there is no assignment to data_out when the row is 0.
Try:
data_out(i) <= '1' when unsigned(data_out_array(i)) /= 0 else '0';
That's what I had intended to type...good catch.
KJ
.
- References:
- How to "or" a generic array of std_logic_vector ?
- From: HansWernerMarschke
- Re: How to "or" a generic array of std_logic_vector ?
- From: KJ
- Re: How to "or" a generic array of std_logic_vector ?
- From: Andy
- How to "or" a generic array of std_logic_vector ?
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