Re: ASIC and FPGA : inferring multiplier

Pasacco wrote:
In the log file,

..
Processing 'TOP_DW02_mult_0'
...
Some adders and multipliers are inferred.
The design is 120 MHz in FPGA and 450MHz in ASIC.
So, it seems the flow is okay. thank you very much for reply.

You should also see somewhere what multiplier architecture was
really selected. If DC+DW are recent versions it should be
either csa (Cassy-Save array) that does not need DW license
or pparch (Delay-optimized Booth Wallace) which needs DW
license.

You need something like this for DW in the synthesis scripts

set synthetic_library [list dw_foundation.sldb]
set link_library [concat $target_library $synthetic_library]
set search_path [concat $search_path [list \
[format “%s%s” $synopsys_root “/dw/sim_ver”]]]
set synlib_wait_for_design_license [list “DesignWare”]

and to force faster multiplier (if the constraints are not
finished) something like this.

set_implementation pparch [list my_multiplier]


There are also many different adder architectures available
(rpl,cla,pparch,clf,bk,csm,rpcs at least). So the frequency
you achieved could be much higer with some synthesis script
changes.

--Kim
.

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