Re: rising edge of the clock and data
- From: john <conphiloso@xxxxxxxxxxx>
- Date: Tue, 25 Mar 2008 08:50:34 -0700 (PDT)
On Mar 25, 11:02 am, Pieter Hulshoff <phuls...@xxxxxxxxx> wrote:
john wrote:
Its the output waveform. DCLK is a 50 percent duty cycle 1MHz clock.
If your output is both clock and data, consider inverting the clock output..
Alternatively, use a negative edge clocked FF at the output with a postive edge
clocked FF right before it (so you have a FF to FF transfer without logic in
between; should work fine at half clock cycle).
Kind regards,
Pieter Hulshoff
Hi,
Should I add the positive edge FF before the negative edge clock for
CLOCK output or the data output?
John
.
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