Re: synthesizing 'rightof or 'succ



On Sat, 10 Nov 2007 03:37:30 -0800, Neha <neha.karanjkar@xxxxxxxxx>
wrote:

I have an FSM with 32 states. States 0, 1 and 31 are unique, and the
rest are basically doing the same thing.

As Mike said, it's probably best to use a counter to cope
with this kind of thing.

I usually prefer to have a downcounter and leave it counting
unconditionally, synchronously loading it with a timeout value
whenever necessary. This commonly gives rise to more compact
and cleaner logic than a FSM that decrements the counter in
various different places - although these days the tools are
pretty good at recognising such shareable increment/decrement
operations.

My code would look something like this. Note the use of a
variable (even though it's not terribly convenient) to
hide away the downcounter entirely within the process
that needs it.

...
process (clock, reset)
variable timer, next_timer: unsigned(...);
begin
if reset = '1' then
--- do all your resets, including...
state <= t0;
timer := to_unsigned(0, timer'length);
elsif rising_edge(clock) then
next_timer := timer - 1; -- count down, by default
case state is
when t0 =>
.....
state <= t1;
when t1 =>
..... make decision to go into timed state tt
state <= tt;
next_timer := to_unsigned(DELAY, timer'length);
when tt =>
if timer = 0 then
-- timer has run to completion
state <= t31;
end if;
when t31 =>
...
end case;
timer := next_timer;
end if;
end process;

An alternative would be to write your own SUCCESSOR() function
and use that in place of 'SUCC. This function would be quite
clunky, but it would at least hide away all the messy detail
so that you can get the desired effect in your FSM.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
.



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