Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal
- From: JK <krishna.janumanchi@xxxxxxxxx>
- Date: Fri, 26 Oct 2007 11:55:11 -0000
On Oct 26, 2:21 pm, Pieter <pieter.huy...@xxxxxxxxx> wrote:
Hi,
I had already checked if my device supports the clock range, witch
is now problem for a spartan 3. I connected also the LOCKED_OUT signal
to the reset pin, but when I do that is just stays in reset.
Maybe it's better to explain how I now reset the DCM.
I've got two counters, one counts the incoming clock signal and the
other one counts the outgoing signal. With another clock I made a
window that is high for a time, in this time the counters will
count up with each rising edge of the in- or outgoing clock signal,
depends on the counter. Afther this period I will clock the two count
value in and compare them to each other. If the difference is more
than 10, then I will reset the DCM. I also added an counter that make
sure that the reset pin stays high for an certain amount of clock
cycles.
Also the DCM will reset when there's now dvi input signal anymore,
when status bit is high and there's also an external reset
possibility.
VHDL code:
fault_int <= (not dvisyncdetect or status(1)or DCMreset or
DCM_1_reset);
DCM_1_reset <= not (output_OK and DCM_locked) and delaycounter_int(9);
the output_OK is afther comparing the two counters and is the
difference
is to high then will output_OK be zero and is the output clock not
wright.
When I insert the above vhdl code, then the DCM will always be in
reset
mode and I don't get any output clock.
Hope you understanding a bit what I said
Greets
Pieter- Hide quoted text -
- Show quoted text -
Analyze my code and revert back if you need clarification...
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.vcomponents.ALL;
entity test is
port (
clk : in std_logic;
reset : in std_logic;
clkout : out std_logic
);
end entity test;
architecture rtl of test is
component dcmclk
port (
clkin_in : in std_logic;
rst_in : in std_logic;
clkin_ibufg_out : out std_logic;
clk0_out : out std_logic;
locked_out : out std_logic
);
end component;
signal dcm_reset : std_logic;
signal dcm_reset_count : unsigned(3 downto 0);
signal lock : std_logic;
signal lock_reg : std_logic;
signal lock_fall_edge : std_logic;
begin
--instantiate DCM
Inst_dcmclk: dcmclk port map(
clkin_in => clk,
rst_in => dcm_reset,
clkin_ibufg_out => open,
clk0_out => clkout,
locked_out => lock
);
--find out loss of lock when clk changed with falling edge detection
process(clk, reset)
begin
if (reset='1') then
lock_reg <= '0';
elsif rising_edge(clk) then
lock_reg <= lock;
end if;
end process;
lock_fall_edge <= (not lock) and lock_reg;
--dcm reset generation
process(clk, reset)
begin
if (reset='1') then
dcm_reset <= '1';
dcm_reset_count <= 10;
elsif rising_edge(clk) then
-- step 1: normal operation, dcm starts functioning
dcm_reset <= '0';
-- step 2: dcm i/p changed, dcm lock lost
if (lock_fall_edge='1') then
--dcm reset is made high
dcm_reset <= '1';
--dcm reset count is initialized with 10
dcm_reset_count <= 10;
end if;
--step 3: next cycle, dcm reset down counter starts
if (dcm_reset='1') then
if (dcm_reset_count>0) then
dcm_reset_count <= dcm_reset_count-1;
dcm_reset <= '1';
end if;
end if;
-- when dcm reset counter is 0, dcm_reset is '0' -
same as step 1
end if;
end process;
end architecture rtl;
.
- References:
- Prev by Date: Help!!!! Async internal signal generation
- Next by Date: Re: when using generic
- Previous by thread: Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal
- Next by thread: trying to understand someone else's VHDL code
- Index(es):
Relevant Pages
|
