comp.lang.vhdl

Date Index

Conditional module ports, M. Hamed
- Re: Conditional module ports, Andy
  - Re: Conditional module ports, M. Hamed
    - Re: Conditional module ports, Andy
    - Re: Conditional module ports, KJ
- Re: Conditional module ports, Uncle Noah
  - Re: Conditional module ports, Thomas Stanka
    - Re: Conditional module ports, KJ
    - Re: Conditional module ports, Andy
    - Re: Conditional module ports, M. Hamed
    - Re: Conditional module ports, Mike Treseler
    - Re: Conditional module ports, M. Hamed
    - Re: Conditional module ports, M. Hamed
    - Re: Conditional module ports, Brian Drummond
    - Re: Conditional module ports, KJ
Final CFP: 2008 International Workshop on Multi-Core Computing Systems, SP
concatenation N vectors, zlotawy
GENERATE with non contiguous index?, Niv
- Re: GENERATE with non contiguous index?, Niv
- Re: GENERATE with non contiguous index?, Niv
  - Re: GENERATE with non contiguous index?, Brian Drummond
  - Re: GENERATE with non contiguous index?, Brian Drummond
    - Re: GENERATE with non contiguous index?, Niv
    - Re: GENERATE with non contiguous index?, Andy
    - Re: GENERATE with non contiguous index?, Brian Drummond
- Re: GENERATE with non contiguous index?, Martin Thompson
Final call for papers - ISQED08, SVTI
Help!!!! Async internal signal generation, sonny
- Re: Help!!!! Async internal signal generation, Ralf Hildebrandt
when using generic, gharaam
- Re: when using generic, KJ
  - Re: when using generic, Andy
verilog vs vhdl difference, zlotawy
- Re: verilog vs vhdl difference, Jonathan Bromley
  - Re: verilog vs vhdl difference, zlotawy
    - Re: verilog vs vhdl difference, ghelbig
- Re: verilog vs vhdl difference, KJ
- Re: verilog vs vhdl difference, Mark McDougall
  - Re: verilog vs vhdl difference, KJ
  - Re: verilog vs vhdl difference, Andy
    - Re: verilog vs vhdl difference, Marcus Harnisch
    - Re: verilog vs vhdl difference, Andy
    - Re: verilog vs vhdl difference, Marcus Harnisch
    - Re: verilog vs vhdl difference, Andy
- Re: verilog vs vhdl difference, David Spencer
  - Re: verilog vs vhdl difference, Andy
Possible to generate individual cases within a case statement?, longbrmb
- Re: Possible to generate individual cases within a case statement?, Jonathan Bromley
  - Re: Possible to generate individual cases within a case statement?, Andy
    - Re: Possible to generate individual cases within a case statement?, Jonathan Bromley
    - Re: Possible to generate individual cases within a case statement?, longbrmb
    - Re: Possible to generate individual cases within a case statement?, Mike Treseler
    - Re: Possible to generate individual cases within a case statement?, Jonathan Bromley
    - Re: Possible to generate individual cases within a case statement?, Andy
- Re: Possible to generate individual cases within a case statement?, Mike Treseler
- Re: Possible to generate individual cases within a case statement?, Marcus Harnisch
trying to understand someone else's VHDL code, jamesd . snyder
- Re: trying to understand someone else's VHDL code, KJ
- Re: trying to understand someone else's VHDL code, Mike Treseler
  - Re: trying to understand someone else's VHDL code, Andy
DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal, Pieter
- Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal, JK
  - Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal, Pieter
    - Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal, JK
Information, Muruku
- Re: Information, Vagant
8-bit to 32-bit expansion, Vagant
- Re: 8-bit to 32-bit expansion, Pascal Peyremorte
  - Re: 8-bit to 32-bit expansion, Vagant
- Re: 8-bit to 32-bit expansion, Ralf Hildebrandt
  - Re: 8-bit to 32-bit expansion, Vagant
    - Re: 8-bit to 32-bit expansion, Ralf Hildebrandt
    - Re: 8-bit to 32-bit expansion, Vagant
    - Re: 8-bit to 32-bit expansion, Ralf Hildebrandt
question on Quratus and its waveform, Amit
- Re: question on Quratus and its waveform, Mike Treseler
  - Re: question on Quratus and its waveform, Amit
    - Re: question on Quratus and its waveform, Mike Treseler
    - Re: question on Quratus and its waveform, Amit
XILINX CDs, ola@xxxxxxx
- Re: XILINX CDs, Uncle Noah
Re: Help for project, Pascal Peyremorte
florating point and VHDL, Amit
- Re: florating point and VHDL, ghelbig
  - Re: florating point and VHDL, Amit
- Re: florating point and VHDL, Mike Treseler
- Re: florating point and VHDL, Jonathan Bromley
  - Re: florating point and VHDL, Amit
    - Re: florating point and VHDL, Jonathan Bromley
    - Re: florating point and VHDL, Amit
- Re: florating point and VHDL, csantos
- Re: florating point and VHDL, benradu
- Re: florating point and VHDL, benradu
Puncturing 1/2, 2/3, ecc, Kappa
One-element constant array, Amal
- Re: One-element constant array, Jonathan Bromley
  - Re: One-element constant array, Colin Paul Gloster
Why VHDL tutorials kill the brain? Or - where to start?, Vagant
- Re: Why VHDL tutorials kill the brain? Or - where to start?, MikeShepherd564
- Re: Why VHDL tutorials kill the brain? Or - where to start?, Mike Treseler
- Re: Why VHDL tutorials kill the brain? Or - where to start?, Andy Peters
  - Re: Why VHDL tutorials kill the brain? Or - where to start?, MikeShepherd564
Does VHDL cares for R, L, C components?, Vagant
- Re: Does VHDL cares for R, L, C components?, KJ
- Re: Does VHDL cares for R, L, C components?, Andy
Frequency to Time Conversion, alivingstone
- Re: Frequency to Time Conversion, Laurent Pinchart
- Re: Frequency to Time Conversion, Ralf Hildebrandt
- Re: Frequency to Time Conversion, Jeff Cunningham
- Re: Frequency to Time Conversion, Jonathan Bromley
  - Re: Frequency to Time Conversion, alivingstone
    - Re: Frequency to Time Conversion, Amal
    - Re: Frequency to Time Conversion, KJ
    - Re: Frequency to Time Conversion, Amal
    - Re: Frequency to Time Conversion, kennheinrich
    - Re: Frequency to Time Conversion, KJ
    - Re: Frequency to Time Conversion, KJ
FIFO depth, vishnuprasanth
- Re: FIFO depth, naliali
asynchronous design basic, airol
- Re: asynchronous design basic, Jonathan Bromley
  - Re: asynchronous design basic, Marcus Harnisch
    - Re: asynchronous design basic, airol
variables and max frequences, zlotawy
- Re: variables and max frequences, Mike Treseler
- Re: variables and max frequences, KJ
  - Re: variables and max frequences, psihodelia@xxxxxxxxxxxxxx
    - Re: variables and max frequences, Andy
Driving one signal from two processes, Silver
- Re: Driving one signal from two processes, Jonathan Bromley
- Re: Driving one signal from two processes, Mike Treseler
  - Re: Driving one signal from two processes, dhschetz
    - Re: Driving one signal from two processes, Thomas Stanka
    - Re: Driving one signal from two processes, Dave
    - Re: Driving one signal from two processes, Thomas Stanka
VHDL or PCB?, Vagant
- Re: VHDL or PCB?, Mike Treseler
combinationel loop, fpga . vhdl . designer
- Re: combinationel loop, fpga . vhdl . designer
  - Re: combinationel loop, fpga . vhdl . designer
- Re: combinationel loop, Jan Zegers
  - Re: combinationel loop, fpga . vhdl . designer
    - Re: combinationel loop, fpga . vhdl . designer
Is this a VITAL bug?, Peter Spjuth
- Re: Is this a VITAL bug?, Brian Drummond
  - Re: Is this a VITAL bug?, peter . spjuth
Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, Niv
- Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, Mike Treseler
- Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, Jonathan Bromley
  - Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, Niv
    - Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, Jonathan Bromley
    - Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, KJ
    - Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, Niv
    - Re: Procedure and 'LAST_ACTIVE, 'TRANSACTION etc, KJ
Trimming of signals, jonasmaes
- Re: Trimming of signals, Mike Treseler
  - Re: Trimming of signals, jonasmaes
FIR Filter Design, Rob
- Re: FIR Filter Design, csantos
Simulating 8b/10b Encoder/Decoder, ALuPin@xxxxxx
- Re: Simulating 8b/10b Encoder/Decoder, Kai Harrekilde-Petersen
  - Re: Simulating 8b/10b Encoder/Decoder, ALuPin@xxxxxx
is this a toggle ?!, Amit
- Re: is this a toggle ?!, Amit
  - Re: is this a toggle ?!, KJ
    - Re: is this a toggle ?!, Amit
    - Re: is this a toggle ?!, KJ
  - Re: is this a toggle ?!, Mike Treseler
    - Re: is this a toggle ?!, Amit
    - Re: is this a toggle ?!, Mike Treseler
How to implement the bus?, Vagant
- Re: How to implement the bus?, Ralf Hildebrandt
  - Re: How to implement the bus?, Vagant
    - Re: How to implement the bus?, Ralf Hildebrandt
- Re: How to implement the bus?, Mike Treseler
  - Re: How to implement the bus?, Vagant
    - Re: How to implement the bus?, Mike Treseler
- Re: How to implement the bus?, Brian Drummond
State machines, sprocket
- Re: State machines, Mike Treseler
- Re: State machines, Pieter Hulshoff
  - Re: State machines, Brian Drummond
  - Re: State machines, Andy
code coverage in modesim se 6.1f, kalvarajesh2003
- Re: code coverage in modesim se 6.1f, Paul Uiterlinden
Can change UART data port from 8 bits to 16 bits?, Zhi
- Re: Can change UART data port from 8 bits to 16 bits?, Mark McDougall
- Re: Can change UART data port from 8 bits to 16 bits?, Mike Treseler
code coverage in modelsim_se, kalvarajesh2003
- Re: code coverage in modelsim_se, Paul Uiterlinden
Maximum Frequency, zlotawy
- Re: Maximum Frequency, KJ
RS232 post-route simulation issues, jonasmaes
- Re: RS232 post-route simulation issues, KJ
  - Re: RS232 post-route simulation issues, jonasmaes
- Re: RS232 post-route simulation issues, Mike Treseler
process and signal (urgent), Amit
- Re: process and signal (urgent), naliali
  - Re: process and signal (urgent), Vince
    - Re: process and signal (urgent), naliali
    - Re: process and signal (urgent), Vince
    - Re: process and signal (urgent), Amit
    - Re: process and signal (urgent), Amit
    - Re: process and signal (urgent), Amit
- Re: process and signal (urgent), naliali
# ** Warning: /X_FF PULSE WIDTH High VIOLATION ON SET;, cheevu
- Re: # ** Warning: /X_FF PULSE WIDTH High VIOLATION ON SET;, Jonathan Bromley
how to get an output off a debouncer., Amit
- Re: how to get an output off a debouncer., Mike Treseler
  - Re: how to get an output off a debouncer., Amit
    - Re: how to get an output off a debouncer., Mike Treseler
    - Re: how to get an output off a debouncer., Amit
ayuda / help, xecron
Re: integer type output signal is synthesizable?, Thomas Stanka
- Re: integer type output signal is synthesizable?, KJ
  - Re: integer type output signal is synthesizable?, Andy
  - Re: integer type output signal is synthesizable?, Thomas Stanka
    - Re: integer type output signal is synthesizable?, KJ
    - Re: integer type output signal is synthesizable?, Paul Uiterlinden
    - Re: integer type output signal is synthesizable?, KJ
    - Re: integer type output signal is synthesizable?, Paul Uiterlinden
    - Re: integer type output signal is synthesizable?, KJ
    - Re: integer type output signal is synthesizable?, Marcus Harnisch
    - Re: integer type output signal is synthesizable?, KJ
    - Re: integer type output signal is synthesizable?, Paul Uiterlinden
    - Re: integer type output signal is synthesizable?, KJ
    - Re: integer type output signal is synthesizable?, Paul Uiterlinden
    - Re: integer type output signal is synthesizable?, Thomas Stanka
Memory fetch, Chris Maryan
- Re: Memory fetch, Mike Treseler
- Re: Memory fetch, KJ
- Re: Memory fetch, Jim Lewis
- Re: Memory fetch, Jonathan Bromley
  - Re: Memory fetch, Chris Maryan
block/schematic, franco baresi
- Re: block/schematic, Jonathan Bromley
  - Re: block/schematic, David Spencer
Generic multiplexer, VladimirMatvejev
- Re: Generic multiplexer, Andy
Re: PLL Lock Detect, moogyd
Re: Generics and constants, Rob Misc
- <Possible follow-ups>
- Re: Generics and constants, Tricky
  - Re: Generics and constants, Amal
    - Re: Generics and constants, KJ
    - Re: Generics and constants, Amal
    - Re: Generics and constants, Mike Treseler
    - Re: Generics and constants, KJ
    - Re: Generics and constants, Amal
    - Re: Generics and constants, KJ
Re: Does Modelsim work under Windows Vista?, Allan Herriman
- Re: Does Modelsim work under Windows Vista?, Mike Treseler
  - Re: Does Modelsim work under Windows Vista?, Kai Harrekilde-Petersen
    - Re: Does Modelsim work under Windows Vista?, HT-Lab
- <Possible follow-ups>
- Re: Does Modelsim work under Windows Vista?, HT-Lab
resol, John Smith
- Re: resol, KJ
  - Re: resol, John Smith
    - Re: resol, KJ
Re: out ports on the right side, Jim Lewis
- Re: out ports on the right side, Shannon
  - Re: out ports on the right side, Jim Lewis