Re: PLL Lock Detect

On 25 Sep., 19:59, moo...@xxxxxxxxxxx wrote:
Hi,

Not really an (v)HDL specific question, but hopefully there is someone
who can suggest a starting point.

I need to (digitally) generate a lock detect signal for a PLL.

Where do I start?

I assume I would count edges at both the O/P and reference clock and
then compare the two count values. This leads to a couple of
questions.
- I want the counts to be the same when the PLL is locked. Therefore I
need to restart the counts together
- The counts should be the same for N clock cycles before lock becomes
active, but we should loose lock when the counts become different.

Any suggestions or pointers greatly appreciated.

Thanks,

Steven

Is it an FPGA internal PLL or an external ?

Rgds
Andre

.

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