Re: Glitch Problem

On Sep 13, 4:04 am, Steve.Minsh...@xxxxxxxxx wrote:
Hi

I'm developing a Pulse-Width-Modulation (PWM) scheme on a Xilinx
spartan 3 digilent demo board to perform sinusoidal current control in
a 3 phase motor. I've managed to just about get it working apart from
some strange behaviour where something unknown causes a glitch and
this results in a spike in the current in the motor. The interesting
thing is that during the course of trying to find the problem I have
wired various signals internal to the FPGA to output pins to view on a
scope. In doing this (purely connecting internal signals to the IO
pins) the problem has been cured. I'm guessing therefore that this is
a timing issue or could anyone suggest an alternative cause? Is there
a method of setting timing constraints for internal signals in ISE?
(I can set timing constraints for inputs and outputs but can't find
anything to set timing constraints on internal signals)

The block proceeding the signal which is routed to the IO (to cure the
problem) is a lookup table that compares a timer count signal with
duty times and produces a control signal. The VHDL code for this
block is:

begin
process (count, d1, d1_d2)
begin
if (count <= d1) then
vector_control <= "00";
elsif ((count > d1) AND (count <= d1_d2)) then
vector_control <= "01";
else vector_control <= "10";
end if;

end process;

ISE has implemented this as some magnitude comparators and a ROM
(implemented in a LUT rather than blockram)

This part of the system is combinatorial and not clocked but inserting
a clocked register on the output of this block does not help.

Any suggestions or comments greatly appreciated.

Steve Minshull

About the only thing your problem and solution would indicate is a
timing problem. I suspect the above code is not your problem if
putting a register on the output is not fixing it. You do have timing
constraints, and are running static timing analysis, right?

How long (relative to a clock period) are your glitches lasting?

Also, the (count > d1) is superfluous in the elsif condition. It is
implied by the elsif and the previous condition. It should get
optimized out anyway by the tool, but...

Andy

.

Relevant Pages

  • Glitch Problem
    ... a 3 phase motor. ... In doing this (purely connecting internal signals to the IO ... a method of setting timing constraints for internal signals in ISE? ...
    (comp.lang.vhdl)
  • Re: Sequentially syncrhronous
    ... Having 'extra' signals in the sensitivity list will not result in any ... suggest looking more closely at the synthesis logs as well as timing ... VHDL or Verilog) is not the same as software. ...
    (comp.arch.fpga)
  • Re: timing ...
    ... I have few days to understand this timing thing and implement it using ... between any two signals ... parameter table define Tcop as being the delay from the input signal ... be stable for some period of time before the rising edge ...
    (comp.lang.vhdl)
  • Re: OV7620 image sensor interface with FPGA headache
    ... >pullup resistor and make sure the timing specifications are met and BAM! ... I got the acknowledge signals and the PCLK frequency has doubled ... It is NOT meant as a standard video camera. ... >I'm wondering if this is because the sampling clock my FPGA use is ...
    (comp.arch.embedded)
  • Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic -
    ... As with timing problems on a real board, the results you see with a timing ... all signals except for those that truly do require multiple drivers. ... MY_PROC: process (clk, rst) is ... Whatever is put in for "rst" will be the reset, and if you try to put ...
    (comp.arch.fpga)