Re: Modeling pullup on the input


"YK" <ykmayee@xxxxxxxxx> a écrit dans le message de news: 1185568557.877163.151490@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Jul 27, 10:15 am, "ast" <a...@xxxxxxx> wrote:
"YK" <ykma...@xxxxxxxxx> a écrit dans le message de news: 1185495755.824311.59...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx





> Hi

> Is there a way to model a pullup on the input of a module without
> using any internal signal like the verilog-HDL pullup.

> If I model using a pullup map as below:

> test_ipd <= pullupmap(TO_X01Z(test))

> constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
> 'H');

> I can see that test_ipd is pulled up when test is 'Z'. But is it
> possible to model such that pullup can be seen on "test" signal
> instead of "test_ipd".

State H (weak high) of type std_logic- Hide quoted text -

- Show quoted text -

Thanks for your reply. Pardon me if I didn't understand the reply
correctly. Let me explain my problem in detail.

I am trying to write a simulation model for an input buffer with pull
up resistor. I want to model the pullup on the input port of a module,
not on the signal in the module.

The module is written below(didn't include the port delays and path
delays section)

entity inbuf is

port(PAD : in std_logic;
Y:out std_logic);

end entity;

architecture buf_arch of inbuf is
pad_ipd : std_logic;
begin

pad_ipd <= 'H';
pad_ipd <= pad;
vitalbehavior : process(pad_ipd)--in this vitalpathdelay section is
not included
variable Y_zd : std_logic;
begin
Y_zd := TO_X01(pad_ipd);
end process

end buf_arch;


Now if the user simulates using this simulation model, he will able to
see the pullup on the pad_ipd signal only, not on the pad signal
directly. Again the pad_ipd is added just for user to be able to see
the pulledup input signal. Is there a way to show the pullup on "pad"
to the user.

--------
You dont see the pull up on PAD because in your model PAD is an "input" port.
PAD has to be an "inout" port according to me.

I would suggest the following code:

entity inbuf is

port(

PAD : inout std_logic;
Y :out std_logic);

end entity

architecture buf_arch of inbuf is
begin

PAD <= 'H';
Y <= TO_X01(PAD);

end buf_arch;



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