Re: How in VHDL do I write formatted spreadsheet file of my signals?
G Iveco schrieb:
After reading textbook for a while, I can't figure out how to write
formatted
texts. It seems this language is so complicated but fails to address the
simplest
tasks.
Verilog-XL was even worse ;-) If you use the C-like functions of Verilog
2000 you should have a look at the C-like text-I/O functions for VHDL:
<
http://bear.ces.cwru.edu/vhdl/>.
Ralf
.
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