Problem with simple VHDL piece of code

Hi all,

I'm wondering if any VHDL expert out there can tell me why the
following piece of code isn't working. It should be a simple clock
divider, enabling the CE signal on every counter'th pulse. However the
counter increase line counter := 1+ counter does not increment the
variable. If I change the 1 to for example 20 it stays 20 throughout
the simulation. I'm sure the input signals are correct... Any
suggestions would be helpful.

Thanks,
Jaco

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begin

process (clk)
variable counter : integer :=0;

begin
if (clk'event and clk = '1') then
counter_out <= counter;

if rst <= '1' then
counter := 0;
ce_out <= '1';
end if;

if start <= '1' and rst <= '0' then
if counter < counter_top + 1 then
ce_out <= '0';
counter := 1 + counter;
else
counter := 0;
ce_out <= '1';
end if;
else
ce_out <= '1';
end if;
end if;
end process;


end Behavioral;
==================================

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