Re: Multiple sources ??? Example vhdl code - anyone can help ???

On 24 Mai, 19:41, "adamjon...@xxxxxxxxx" <adamjon...@xxxxxxxxx> wrote:
Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this function.

Here is full source code:

--
Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this error.

Here is full source code:

-- file box1.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box1;

architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- file box2.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box2;

architecture box2 of box2 is
begin
PR:process(data,c)is
begin
if c='0' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- filebox12.vhd (ERROR ????? - HOW TO WRITE IT ANOTHER WAY ???)
library IEEE;
use IEEE.std_logic_1164.all;

entitybox12is
port (c: in STD_LOGIC;
d : out STD_LOGIC);
endbox12;

architecturebox12ofbox12is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

signal data1 : STD_LOGIC_VECTOR(7 downto 0);

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

endbox12;

I'll we be thankfull for any help.

Hint: you can read from an in or inout port but not from an out port.

Three possible solutions for your problem:
1. remove data from the sensitivity list in box1 and box2 and declare
data as an out port

2. declare data1 as an inout port in box12

3. rewrite your code using multiplexers if possible which is highly
preferred.

regards

Wolfgang

.

Relevant Pages

  • Re: Multiple sources ??? Example vhdl code - anyone can help ???
    ... problem with multiple sources (exactly I've got error 'Signal data1 ... resolve this function. ... end component box1; ...
    (comp.lang.vhdl)
  • Re: Cant join a domain
    ... Attempting to resolve name to IP address... ... TCP port 42: NOT LISTENING ...
    (microsoft.public.windows.server.active_directory)
  • Re: Cant join a domain
    ... Attempting to resolve name to IP address... ... TCP port 42: NOT LISTENING ...
    (microsoft.public.windows.server.active_directory)
  • DCPromo and VPN fails
    ... Querying target system called: ... Attempting to resolve IP address to a name... ... TCP port 135: ...
    (microsoft.public.windows.server.active_directory)
  • Re: Add a new DC to a new branch
    ... A Cisco router serves as DHCP server ... Querying target system called: ... Attempting to resolve IP address to a name... ... TCP port 135: ...
    (microsoft.public.windows.server.active_directory)