Re: Calling functions declared in an entity

Andre wrote:

Dear all,

In VHDL it is possible to declare the following entity:

File Foo.vhd contains

entity Foo is
generic
(
Width : in natural := 3
);
port
(
Clock : in std_logic;
SIn : in std_logic
);
function Do_It return std_logic
end Foo;


Now I want to use this entity in Test.vhd

entity Test is
port ( .... )

architecture rtl of Test is

component Foo is
generic
(
Width : in natural := 3
);
port
(
Clock : in std_logic;
SIn : in std_logic
);
function Do_It return std_logic
end component;

begin

i_Foo : Foo
generic map
(
Width => 3
);
port map
(
Clock => Clk1,
SIn => Test
);

External <= Do_It; -- Error, unknown

end;

The question is (finally:):
- How can I use the Do_It function in the other entity?

You can't. Put the function in a package instead. By the way: you have put
the subprogram declaration in the entity. In stead, you should put the
subprogram body there. See example below. I would expect your file Foo.vhd
to result in an error message like "Subprogram 'Do_It' declared at line 10
has no body".

- If I can't, what is the use for the declaration part in an entity?

The declarations made there will be visible in all architectures of that
entity. Trivial example:

ENTITY ent_item_decl IS
PORT
(
i : IN bit;
o : OUT bit
);
FUNCTION f -- entity-item-declaration
(
i : bit
) RETURN bit IS
BEGIN
RETURN NOT i;
END FUNCTION f;
END ENTITY ent_item_decl;

ARCHITECTURE rtl OF ent_item_decl IS
BEGIN
o <= f(i);
END ARCHITECTURE rtl;

ARCHITECTURE rtl_another OF ent_item_decl IS
BEGIN
o <= f(i);
END ARCHITECTURE rtl_another ;

I've never used an entity-item-declaration. No idea whether it is
synthesizable. The most common way is to put the function in a package, or
in the architecture (if there is only one).

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
.

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