VHDL Library Madness




"Martin Thompson" <martin.j.thompson@xxxxxxx> wrote in message
news:u647jtai1.fsf@xxxxxxxxxx
Hi Ben,

Do you have any clout in Xilinx to get all the standard templates and
appnote code to do that instead of _unsigned and _arith all over the
place?

Wow, if only! :-)

I have the power to complain vociferously about it in internal code reviews,
which I exercise at every opportunity. I also have the power to file CRs on
the documentation, but it's a tough thing to get changed. The worst
offenders are the XST manual and the Synthesis and Simulation Design Guide.

But the XST engineers are too busy developing XST to be able to justify
spending time on replacing one working code example A with another working
code example B, whatever the relative merits of A and B. You can't expect a
technical writer to do it because it needs to be tested and working before
it goes into the documentation.

And when some new code example needs to go into the documentation, of course
the first thing that happens is the author goes and fetches some existing
example as a starting point, so they can make sure they're consistent with
the prevailing practice. Whoops!

Appnote code is the hardest to fix. When code originates within the tools
and/or IP organisations it's usually gone through a review process against
some coding standard. Appnotes often come from outside this bubble and the
release process for those, to be honest, seems to be optimized for "getting
working stuff to customers" rather than "checking for rigorous compliance
with some standard or other".

Here are the raw numbers of occurances of the different library names in as
of the latest build I have installed:

xst.pdf sim.pdf
std_logic_unsigned: 61 22
std_logic_signed: 8 5
std_logic_arith: 13 5
numeric_std: 14 3

Sheesh. If enough people offer to buy me beer, I will sit down one evening
(or several!), go through all the example code which has "bad" libraries,
upgrade it to numeric_std, re-test the code against the latest tools, and
submit my changes. This does *not* guarantee that the documentation will end
up fixed, but I'm willing to try it anyway. Be prepared to add your names to
some sort of petition when I go to file the CR.

Can people let me know if there are any other documents I've missed that are
suffering from VHDL Library Disease, or any other pertinent information that
might save me some of the pain from my impending martyrdom? :-)

Cheers,

-Ben-


.



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