Re: VHDL syntax

Did you check the post-synthesis simulation?
The workaround with a variable may not work correctly.
The parsers may not notice something suspicious but netlist can be
incorrect.
(Vendors usually talk about next release if something is not working in the
current one).

Best Regards,
Slawek

"Grumps" <grummps@xxxxxxxxxxx> wrote in message
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Slawek wrote:
"Grumps" <grummps@xxxxxxxxxxx> wrote in message
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Hi
I have an issue with a synthesiser and I'm not entirely sure of the
response I recevied from the vendor's support team.

One particular line of code reads:
i(7+(8*c) downto 8*c) := ip;
Where c is a signal.

One of our synethesisers flags this as an error and says the bounds
must be constants. The solution is to declare c as a variable.
Two other synthesisers (inc. Synplify) don't flag this as an error.

If we are declaring c incorrectly, then fair enough. But we are
thinking about moving to using FPGA devices which are supported by
their free software. If we have to re-write a lot of our code, then
we won't make the move.
Thanks for any comments.

Hi,
the slice range should be constant. Dynamically changed slice range
used to be reported as error even in Synplify (year or two ago).
I am not using Synplify recently and I am not sure if it is really
supported in the latest version. I am quite sure that it is not
supported in XST or similar free FPGA synthesis tools.

Thanks for the reply.
But surely neither a signal nor a variable are constants. Yet defining c
as a variable prevents the error.
Ah well. The vendor in question has replied and said that they will see if
a change can be made to the next release.



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