Re: long/short sensitivity list


"titi" <titi@xxxxxxxxx> wrote in message
news:esjgpf$117t$1@xxxxxxxxxxxxxxxxxxxxx
In the sample code here after, the sensitivity list is (Reset,Load,F).
Would it be correct to write (Reset,F)?
Why, why not?

machin : process(Reset,Load,F)
begin
if Reset ='1' then
En1 <= '0';
En2 <= '0';
elsif F'event and F ='1' then
En1 <= Load;
En2 <= En1;
end if;
end process;

The correct sensitivity list is "Reset, F". The reason is because nothing
happens when the signal "Load" changes (as you have in your list). To see
for yourself, simply take a walk through the code holding all inputs
constant and you'll see that the only way you can get to the lines
En1 <= Load;
En2 <= En1;
are if there has been a rising edge detected on signal 'F'. So change
'Load' all that you want all by itself and it will not affect the outputs of
the process 'En1' and 'En2'. By adding 'Load' to the sensitivity list,
you're telling the simulator to execute this process whenever 'Load'
changes. But as you've seen, none of the outputs will change as a result of
a change in 'Load' so you've caused the simulator to needlessly waste cycles
evaluating something for no reason.

On the plus side, there are much worse things than wasting CPU cycles, the
design as written will simulate and synthesize just fine. There are much
worse things. Ask yourself what would happen if you left 'Reset' out of the
sensitivity list instead (by accident). In that situation, the asynchronous
resetting of 'En1' and 'En2' would not occur. If your clock signal 'F'
happens to be running while 'Reset' is true then the resetting will occur at
the next rising edge of 'F' (i.e. a synchronous reset) but if it's not then
the code after 'if Reset='1' then...' will never execute. Most any
synthesis tool will report this as a warning about an incomplete sensitivity
list and will implement what you intended AS IF you had included 'Reset' in
the sensitivity list. Things like this cause simulation results and actual
implementation results to differ.

I'll also take a moment to encourage the use of
if rising_edge(F) then...
as being clearer than
if F'event and F ='1' then

Kevin Jennings


.

Relevant Pages

  • Re: Power-On Reset
    ... >We don't want to load either of the xtal pins, ... I just did the RESET logic inside a CPLD. ... You can load the osc-out pin of the 8051 with a CMOS gate without causing ... fix a broken subtract. ...
    (sci.electronics.cad)
  • Re: Power-On Reset
    ... >We don't want to load either of the xtal pins, ... I just did the RESET logic inside a CPLD. ... You can load the osc-out pin of the 8051 with a CMOS gate without causing ... fix a broken subtract. ...
    (sci.electronics.design)
  • Re: Register with a default Value
    ... Now it is working in simulation, I hope to test it on the board today. ... Port (clk: in STD_LOGIC; ... reset: in STD_LOGIC; ... load: in std_logic; ...
    (comp.lang.vhdl)
  • Re: WPC GI power draw causes resets?
    ... As a control test remove the load of the controlled lights, ... reset on both flippers again, and I confirmed that removing all power ... power is used in the GI circuit. ...
    (rec.games.pinball)
  • Re: Modelsim error: Cannot read output pain
    ... Synthesis Warning: Reset signal 'status' is not in the sensitivity list of process 'proc'. ... You are confusing the synthesis tool, and it is probably not using the builtin FPGA reset resources. ... Because you have a procedure with status as a parameter, the synthesis tool thinks this is a source signal, and that it should therefore be in the sensitivity list. ... If you explicitly set the value of status within the reset portion of the process, you will not need to put it into the sensitivity list. ...
    (comp.lang.vhdl)