Re: equivalent of defparam in vhdl.

Hi,

First of this is only for simulation and not for synthesis.
Secondly, i dont think i can use the -g option, as the problem is with
wrapper + smart models rather than actual vhdl files.

thanks....

Ajeetha wrote:
Hi KK,
If this is for Synthesis, it is a bad style - usually defparam is
unsupported in synth tools. If it is for pure simulation alone,
simulators provide a way to override generics from command line.
Typically the option is "-g".

Read your tool's doc for more.

HTH
Ajeetha, CVC
www.noveldv.com
www.systemverilog.us

kk wrote:
For one of my program, i use defparam in verilog to set a parameter
which is one level below the hierarchy. I've three modules A, B, C. The
C is instantiated in B, B in A. There is a parameter in C which is not
brought out to B. I dont have the permission to modify B and C by any
chance. In verilog i can set the parameter by using a defparam
statement in A.
Is there way i could do this in VHDL, if all the three are in VHDL.

thanks in adv.

.

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