Re: Stupid Newby Question: VHDL/CPLD Shift Register Reset Problem

In message <1151676242.704035.239970@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
"dhudson01@xxxxxxxxx" <dhudson01@xxxxxxxxx> wrote:

Follow up:

I submitted a WebCase to Xilinx describing my problem and worked with
some others as well trying to resolve this issue. I ran behavioral and
post-fix simulations and they showed that the code should work as
intended. I modified the pin out so that instead of general I/O pins,
my clock and reset signals were connected to the GCK2 and GSR pins,
respectively, of the CPLD. Nothing seemed to help.

As I was running out of options, I decided to replace the board that I
was using as a SPI master with an Atmel AVR dev board that I had laying
around. I wrote a quick program that configured the AVR as the SPI
master and transmitted a byte of data. I connected the AVR board to my
Xilinx board and everything worked perfectly!

I have no idea why my original SPI master board didn't play nice. The
clock and data lines looked clean on the scope. Due to my project
schedule, I seriously doubt that I will have time to find out.

You have to use a scope /and/ /probe/ system of sufficient bandwidth.
I often use a 400 megasamples per second 'scope to look at clock
waveforms, but it only shows up real problems when it's used in
equivalent time sampling mode, where the effective sample rate is
much higher. You really need to be looking with a bandwidth of at
least 1 GHz. And that's for devices that are still some way behind
the leading edge of technology.

For a probe, I usually use a 5k1 surface mount resistor on a 50 ohm
cable to the 'scope (which has 50 ohm termination turned on, of
course), with the earth braid kept to less than 1 cm.

If you use an observation system like that, you may discover all
sorts of overshoots, undershoots and multiple transitions. An all
too frequent problem is the clock signal reaching about 1.2 volts,
then changing direction momentarily (under 1 ns) before continuing
to complete its transition. The logic device has enough bandwidth
to see two transitions, in many cases - but, worst of all, you
can't guarantee that all the flip flops in the device will see
them.

If you use an observation system of too low a bandwidth, all this
detail is filtered out.

I exhort everybody to learn and understand transmission line
theory. Once you do, and apply all the remedies whose need then
becomes obvious, development life gets a whole lot easier.

Dave
.

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