Re: Stupid Newby Question: VHDL/CPLD Shift Register Reset Problem

Follow up:

I submitted a WebCase to Xilinx describing my problem and worked with
some others as well trying to resolve this issue. I ran behavioral and
post-fix simulations and they showed that the code should work as
intended. I modified the pin out so that instead of general I/O pins,
my clock and reset signals were connected to the GCK2 and GSR pins,
respectively, of the CPLD. Nothing seemed to help.

As I was running out of options, I decided to replace the board that I
was using as a SPI master with an Atmel AVR dev board that I had laying
around. I wrote a quick program that configured the AVR as the SPI
master and transmitted a byte of data. I connected the AVR board to my
Xilinx board and everything worked perfectly!

I have no idea why my original SPI master board didn't play nice. The
clock and data lines looked clean on the scope. Due to my project
schedule, I seriously doubt that I will have time to find out.

Thanks for taking the time to help me out on this problem.

Later,
Doug

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