Re: VHDL Newbie - Is this a valid statement?

have a nice synthesis

All,

Thank you very much for your help - I didn't realize it until I read
this last line that I hadn't included these signals in my synthesis,
and that was why my FSM was constantly looping when I synthesis.

Once again, thank you all for you quick responses,

nigel

backhus wrote:
Hi Nigel,
your source snippet seems to be ok. If your design isn't time critical
you can leave it the way it is.

To use a reset inside a design as a control signal is a philosophical
question.
But doing the compare inside your fsm increases the number of inputs
unnecessary. Better do that inside your counter and generate a
(synchronous) CountEnd signal there. This may speed up your FSM a little.


Comparing signals to constants is very common in VHDL. If your counter
has only four bits anyway it's sufficient to write
if(counter_q = "1101") THEN
...
end if;

One thing that may bother you is the chosen value. Is cnt_rst a
synchronous or an asynchronous input to the counter? If it's a
synchronous reset your counter may stay one count behind the expected
value (pipelinig effect, check your simulation). To overcome this you
can simply reduce the compare constant.

have a nice synthesis
Eilert




nigel502@xxxxxxxxx schrieb:
Hello,

My goal is to make a step in my FSM that loops until my counter reaches
it's desired value and then moves to it's next step - however I am
having issues detecting it reaching that desired value. I'm assuming
that something is wrong with my conditional statement. Can you compare
a signal against a constant value in VHDL

signal counter_q: std_logic_vector(3 downto 0);
.....
when read_del =>

cnt_rst <='0'; -- signal to reset counter - keep low here

if(counter_q(3 downto 0) = "1101") THEN
next_state <= blah;
else
next_state <= read_del;
end if;

What is the proper way to preform this action?

Thanks in advance


.

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