Re: VHDL Newbie - Is this a valid statement?

nigel502@xxxxxxxxx wrote:

What is the proper way to preform this action?

You haven't provided enough information.

"...having issues detecting it..." - what exactly do you mean? Compile errors? Or just doesn't appear to work? Does counter_q increment?

You haven't explained how you are clocking counter_q, or the state machine itself! How/where are you incrementing counter_q?

As an aside, I prefer to assign default values to signals to reduce the number of 'else' statements required - which can be quite significant in large state machines!

ie.
next_state <= state;
case (state) is
when read_del =>
if counter_q(3 downto 0) = "1101" then
next_state <= blah;
end if;

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
.