VHDL Newbie - Is this a valid statement?

Hello,

My goal is to make a step in my FSM that loops until my counter reaches
it's desired value and then moves to it's next step - however I am
having issues detecting it reaching that desired value. I'm assuming
that something is wrong with my conditional statement. Can you compare
a signal against a constant value in VHDL

signal counter_q: std_logic_vector(3 downto 0);
......
when read_del =>

cnt_rst <='0'; -- signal to reset counter - keep low here

if(counter_q(3 downto 0) = "1101") THEN
next_state <= blah;
else
next_state <= read_del;
end if;

What is the proper way to preform this action?

Thanks in advance

.

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