Re: VHDL Newbie - Is this a valid statement?
- From: Mike Treseler <mike_treseler@xxxxxxxxxxx>
- Date: Wed, 28 Jun 2006 11:16:10 -0700
nigel502@xxxxxxxxx wrote:
Can you compare
a signal against a constant value in VHDL
You can compare a signal's *previous value*.
I find using the *present value* of a process variable
easier to understand.
What is the proper way to preform this action?
That's debatable.
For the way I do it,
see the procedure tx_state in the reference design here:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
.
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