Re: VHDL-200x fixed_pkg synthesis warnings

rnbrady@xxxxxxxxx wrote:
Hi folks

I wonder if anyone can lend me some advice on fixed_pkg_c.vhd? I'm
trying to use it for synthesis, but Synplify gives the message:

Entity port input[1,-14] has negative indices. It is remapped to
positive range [15,0]

Consider converting the top ports (only) to std_logic vector.

This worries me a bit. I'm not sure where it is doing the remapping. If
the warning messages are generated after elaboration, they're possibly
harmeless.

Probably just a bit mapping issue.

So now I'm trying to take the VHDL *netlists* that Synplify Pro
generates, and feed them back into ModelSim to compare to my original
code in terms of functionality. I presume this is the standard method
for validation?

I check the rtl viewer then run
a functional sim on the code,
not the netlist.

-- Mike Treseler
.