Re: Stupid Newby Question: VHDL/CPLD Shift Register Reset Problem


dhudson01@xxxxxxxxx wrote:
Is it okay to bring an external 125 kHz clock signal in on a general
purpose I/O line of the CPLD? This is the input that I am using to
clock my shift register.

Don't think this should be an issue.


The reason I'm asking is because I am having some reset problems when
shifting data on the falling edge of my 125 kHz clock. No reset
problems at all if I change a single line of code to shift from falling
edge to rising edge (see code below).

Someone told me (a Verilog guy, not a VHDL expert) that the problem
could be because I'm not using the "real" system clock as the clock for
my shift register. I could find no other reference that supported that
view. Any thoughts?

Those Verilog guys....snicker

For anyone still reading, the details of my "reset problem" are as
follows:
Following a power cycle, I assert the Reset signal. I then clock in 8
bits of serial data at 125 kHz. The DataReady output signal is
asserted 1 cycle too soon (i.e. it is as if the Count variable is
initialized to '1' instead of '0' at Reset) and my DataOut is off by 1
bit position.

If the Reset signal is asserted again and data is clocked in, the
output is correct. Subsequent data clockings work as expected. The
problem only occurs after power cycling. It is as if I have to clock
in some data before the Reset works correctly after power cycling.

Interestingly, if I change the code to shift on the rising edge,
everything works correctly!

What am I doing wrong? Thanks in advance for any help!

Check the timing from when Reset switches from high to low for the
first time after power cycling and see where it is relative to the
clock and verify that it is meeting the setup time of both the rising
and falling edges of your clock....actually only the edge that you're
using at a given time is important but since you're reprogramming the
CPLD to switch clock sampling edges it needs to be far enough away from
both edges for it to work. I'm guessing that with a 125 KHz clock
though that this probably isn't the problem but worth checking.

Next look to see when that first falling edge after power up really is
occurring. The most likely explanation is that after reset has been
de-asserted (with the above mentioned appropriate setup time) that
you're getting a falling edge on your clock at a time when you're not
quite expecting. That would generate exactly the symptoms that you're
seeing. Also remember that any sort of glitch that can be interpreted
as a falling edge (i.e. something going from >2V to less than ~1.5 V)
can be causing the clocking.

Lastly, look at the signal quality on your clock and make sure that
both rising and falling edges are monotonic. Any sort hiccups in the
'gray zone' (i.e. 0.8 - 2.0 V....I'm assuming TTL logic levels on all
of this by the way) can cause unexpected clocking

KJ

============
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SerialToParallel is
generic(DATA_WIDTH: natural := 8);
Port ( Clock : in STD_LOGIC; -- 125 kHz shift
clock
SerialDataIn : in STD_LOGIC;
Reset : in STD_LOGIC;
DataReady : out STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (7 downto 0);
TestOut : out STD_LOGIC);
end SerialToParallel;

architecture Behavioral of SerialToParallel is
begin
process(Clock, Reset)
variable DataReg : STD_LOGIC_VECTOR (7 downto 0);
variable Count : integer range 0 to DATA_WIDTH;
begin
if (Reset = '1') then
DataReg := (others => '0');
Count := 0;
DataOut <= (others => '0');
DataReady <= '1';
TestOut <= '1';
-- elsif (rising_edge(Clock)) then
elsif (falling_edge(Clock)) then
DataReg := DataReg((DATA_WIDTH - 2) downto 0) & SerialDataIn;

Count := Count + 1;
if (Count = DATA_WIDTH) then
DataOut <= DataReg;
Count := 0;
DataReady <= '1';
TestOut <= '1';
else
DataReady <= '0';
TestOut <= '0';
end if;
end if;
end process;
end Behavioral;

.

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