Re: Counter Issue on FPGA and CPLD
- From: Jonathan Bromley <jonathan.bromley@xxxxxxxxxxxxx>
- Date: Tue, 20 Jun 2006 11:54:44 +0100
On 19 Jun 2006 20:22:04 -0700, "BC" <billcollis@xxxxxxxxx> wrote:
I am new to VHDL and I have a couple of boards that I am experimenting[...]
with using Xilinx ISE 7.1
One is the Spartan-3 board from Digilent which has an XC3S200 FPGA on
it and 50MHz oscillator, the other is a board I made with a Xilinx
XC9572 84 pin CPLD on it and a 10MHz oscillator.
With either board I can successfuly create schematic based asynchronous
counters using D type flipflops to divide the clocks down. On the S3
board I can also write code such as this to create a divide by 10.
HOWEVER, this code does not work on the CPLD board the output is close
to a divide by 2, but not completely regular. I have also tried a
schematic design for a synchronous divide by 10, however that doesnt
work in the CPLD either.
I'm sure its something obvious that I'm missing, something to do with
the clocks on the CPLD maybe???
No guarantees of course, but in my experience this is usually caused
by one of two problems:
1) Check this first because it's easy to fix:
Is your clock input really going to one of the CPLD's dedicated clock
input pins? If not, you may have issues about the timing of clock
signal distribution that give rise to hold time violations. This
can easily make counters and other synchronous logic go
horribly wrong, even with a slow clock.
2) This one is more likely to be the problem, but more work to fix:
Your CPLD board is "home-made", yes? Then I suspect the
problem may be related to ground integrity ("ground bounce").
CPLD outputs are pretty brutal things; they can drive large amounts
of current with very rapid rising and falling edges. If these outputs
are driving something with significant capacitance (for example,
a cheap-and-nasty x1 'scope probe, or a long piece of wiring) then
the current pulse that flows in the GROUND pins of the CPLD as
the result of 1->0 output transitions can be very large and very
fast. The ground wiring, if it's not a solid ground plane on
a PCB, will have inductance; rapid current changes flowing
in this inductance will cause voltage spikes on the ground
pins of the CPLD. I have often seen this effect give rise to
spurious clocking of a device. It used to be a terrible problem
when students used CMOS GAL22V10 devices for experiments,
and they put them on stripboard. Combinatorial logic worked
beautifully, clocked logic was almost always broken.
The only truly reliable solution to (2) is a PCB with a
really good ground plane. However, you can go a long
way to fixing it by adding small resistors (50 to 100 ohm)
in series with each output pin of the CPLD, TAKING GREAT
CARE TO PUT THE RESISTORS AS CLOSE TO THE PIN
AS POSSIBLE. In this way, the currents flowing in each
output are limited - it's a crude way of restricting the
output slew rate and isolating the outputs from any
large capacitive load.
Please forgive me if this is a red herring!
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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