design compiler optimization

Hi,

Does synopsys design compiler perform a TILOS based circuit
optimization.

TILOS is a iterative circuit sizing tool which selects the critical
path and finds the sensitive gate in the path sizes it and then
continues with the new critical path, published in 1985 by fishburn and
dunlop.

any information and details about this is requested.

if yes, Also can anyone tell me the set of commands to do the
optimization.

thanks,

Mahalingam

.

Relevant Pages

  • Re: design compiler optimization
    ... Does synopsys design compiler perform a TILOS based circuit ... TILOS is a iterative circuit sizing tool, ... See if the optimization results change with lower vaues for the power constraint. ...
    (comp.arch.fpga)
  • design comiler optimization method
    ... TILOS is a iterative circuit sizing tool, published in 1985 by fishburn ... and dunlop. ...
    (sci.electronics.design)
  • design compiler optimization
    ... TILOS is a iterative circuit sizing tool, published in 1985 by fishburn ... and dunlop. ...
    (comp.arch.fpga)
  • optimization using design analyzer, compiler
    ... TILOS is a iterative circuit sizing tool, published in 1985 by fishburn ... and dunlop. ...
    (sci.electronics.cad)