Reading multiple file



I am sure this has been addressed somewhere in this group. My problem
is that I want to read my test vectors from a number of files. I read
the filenames to be read from a "directory". I can read the first set
of data all right from all the files. However, the 2nd set of data is
never read correctly. It seems like I am always reading the same data
every time. In other words the files are accessed from the very
beginning time and again. Here's the code:

ENTITY read_input_data IS
PORT(
clk : IN std_logic;
frame_num : IN integer;
sysrst_n : IN std_logic;
ts_en : IN std_logic;
tscount : IN integer;
tscount_ahead : IN integer;
transmit_data : OUT unsigned (7 DOWNTO 0)
);

-- Declarations

END read_input_data ;

--
library std;
use std.textio.all;
ARCHITECTURE spec OF read_input_data IS
signal flag : std_logic;
BEGIN
process(sysrst_n, clk, flag)
variable end_of_file : boolean;
variable dat1 : unsigned( 7 DOWNTO 0);
variable in_line : line;
variable comment : boolean;
-- Here's where we declare a directory which contains the input
-- stimulus files to design under test.
file directory_input : text open read_mode is
"C:\backplane_stimulus_directory";
variable input_file_name : line;
variable input_file_name_length : natural;
variable open_status : file_open_status;
file stimuli : text;
begin
-- Here's where we start reading from a directory of files.
file_loop : while not endfile(directory_input) loop
readline(directory_input, input_file_name);
-- open the file for reading
file_open(open_status, stimuli, input_file_name.all, read_mode);

if (open_status /= open_ok) then
report file_open_status'image(open_status) & " while opening file "
& input_file_name.all & " - file skipped"
severity warning;
next file_loop;
end if;

--read data from files listed in the directory
if not endfile(stimuli) then
--read first line
readline(stimuli, in_line);
--a procedure that is defined elsewhere
read_hex(in_line, dat1, comment);
if (flag = '1') then
next file_loop;
end if;
end if;
end loop file_loop;

if(sysrst_n = '0') then
transmit_data <= (others => '1');
flag <= '0';
elsif(falling_edge(clk)) then
-- READ and OUTPUT DATA
if (tscount >= 0 and ts_en = '1' and frame_num >= 0) then
transmit_data <= (others => '1');
flag <= '0';

--put data on bus
for i in 0 to (num_chi_ts_used - 1) loop
if (tscount_ahead = chi_timeslot_number(i)) then
transmit_data <= dat1;
flag <= '1';
end if;
end loop;
else
transmit_data <= (others => '1');
end if;
end if;
end process;
END ARCHITECTURE spec;

Can anyone help please?

Thanks.
naveen

.



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