Re: Dual data rate in Xilinx WebPACK 7.1
- From: "Ben Jones" <ben.jones@xxxxxxxxxx>
- Date: Thu, 2 Mar 2006 14:10:00 -0000
"Rafal Pietrak" <rp@xxxxxxxxxxxxxxxxxx> wrote in message
news:pan.2006.03.02.11.03.50.149669@xxxxxxxxxxxxxxxxxxxxx
Couldn't help it :) Gave it another thought.... HDL semantics (or may be
just WebPACK synthesizer implementation) look even stranger to me, now.
That is usually a sign of progress. :-)
The point is, that following your advice: if I were *reading* the HDL
code, I'd imagine a 'priority decoder':
1) when reset_active --> do something...
2) when *it's*not*, but rising_edge(clk) occur --> do something else ...
3) when this isn't happening either, but there is a falling_edge() --> do
yet another thing.
Priority encoders do exist.
Granted. However, there's a world of difference between edges and levels
when it comes to synthesis. A priority encoder is a bit of combinatorial
logic that works as you describe above, but it works on levels, not edges:
if reset = '1' then
output <= "00";
elsif heads = '1' then
output <= "01";
elsif tails = '1' then
output <= "10";
else
output <= "11";
end if;
The difference is that combinatorial logic can be imagined as executing in
zero time, whereas rising_edge() and falling_edge() immediately imply some
notion of the passing of time. When a synthesis tool wants to build a piece
of combinatorial logic, it can basically use any combinatorial building
block that it wants. However, the synchronous building blocks in FPGAs (and
most digital systems) are rather more limited.
The task "transfer the value of signal A to signal B on the rising edge of
signal Clk" requires a register element - nothing else can do the job. If
you add to that "unless reset = '1', in which case assign '000' to signal
B", then a synchronous reset of that register is required. If instead you
prepend "if reset = '1' then B <= '000' else", then an asynchronous reset of
that register is required. If you go asking for
resets/sets/clears/clock-enables that aren't available, then the tool will
either try to emulate them (e.g. by adding AND gates) or will give up. The
same is true if you try to describe a transparent latch, or a double-edged
register, when such a thing isn't available in the technology.
So it looks like I have to be *very* *very* cautious when writing HDL.
Don't be too cautious - you'll never get any work done! Mostly, it comes
down to learning the necessary idioms of the language (in this case,
synthesizable VHDL). Once you've written, simulated and synthesized a few
circuits you'll wonder what you ever thought was hard about it... :)
Cheers,
-Ben-
.
- References:
- Re: Dual data rate in Xilinx WebPACK 7.1
- From: Rafal Pietrak
- Re: Dual data rate in Xilinx WebPACK 7.1
- From: Ben Jones
- Re: Dual data rate in Xilinx WebPACK 7.1
- From: Rafal Pietrak
- Re: Dual data rate in Xilinx WebPACK 7.1
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