Re: Problem while updating the output---Help required



Hello

I am using ModelSim for simulation. The output is ok when it is 0 but
when it should be one it is X dont care...
however the signal 'clk_tmp_reg' has correct waveform. I am assigning
clk_reg <= clk_tmp_reg to have the output but it is not following the
clk_tmp_reg.

if u need test bench it is below


Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.ALL;

entity Power_reg_tb is end;

architecture tb of Power_reg_tb is

component Power_reg
port (
clk, rst : in std_logic;
sys_clk : in std_logic;
core_power_reg : in std_logic_vector(8 downto 0);
core_clock_reg : in std_logic_vector(8 downto 0);
proc_power_bit : in std_logic;
proc_clk_bit : in std_logic;
power_reg : out std_logic_vector(9 downto 0);
clk_reg : out std_logic_vector(9 downto 0)
);
end component;

signal clk, rst : std_logic := '0';
--signal sys_clk : std_logic := '0';
signal core_power_reg : std_logic_vector(8 downto 0) := "000000000";
signal core_clock_reg : std_logic_vector(8 downto 0) := "000000000";
signal proc_power_bit : std_logic := '0';
signal proc_clk_bit : std_logic := '0';
signal pwr_reg : std_logic_vector(9 downto 0);
signal clk_reg : std_logic_vector(9 downto 0);

for U1: Power_reg use entity work.Power_reg(rtl_power_reg);

begin

U1: Power_reg port map ( clk, rst, clk, core_power_reg, core_clock_reg,
proc_power_bit, proc_clk_bit, pwr_reg, clk_reg);

rst <= '1' after 30 ns;
clk <= not(clk) after 10 ns;
--sys_clk <= not(sys_clk) after 20 ns;


process
begin
core_power_reg <= "000000010" after 50 ns,
"001000010" after 100 ns,
"100000010" after 150 ns;

wait for 100 ns;

core_clock_reg <= "000000010" after 50 ns,
"000100010" after 200 ns,
"100000010" after 400 ns;

proc_power_bit <= '1' after 100 ns;

proc_clk_bit <= '1' after 150 ns;


wait;
end process;

end tb;

.



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