xilinx and script
- From: "Rick North" <dontreplytothisaddy@xxxxxxxxxxx>
- Date: 8 Nov 2005 14:12:56 -0800
Hi all,
Will Xilinx bundle tcl in Xilinx ISE? I know that they have Pearl, but
all other development tools I use (modelsim, synplify etc) have support
for tcl.
Is there a strong will in the community to use script or are people
satisfied to click and wait and click their way through the design
steps?
I have just started to script my way through my design which is quite
large and has a bunch of vhdl files. The thing I have trouble with at
this point is to order the files in hierarchy and compile order for
synthesis. So far I have done it by hand but I hope there is a better
way. I have seen emacs do it in vhdl mode but I don't know how to
extract it. Has any of you done this or should I let a design tool do
it for me?
Regards,
R N
.
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