Re: RTL 10 Commandments

Hi Beanut,

My comments below:

"Beanut" <fourbeans@xxxxxxxxx> writes:

> Here's a list of rules I've compiled over time from experience and web
> sites like this one. Please provide feedback. My target is for
> engineers and students new to VHDL/Verilog who might not know what many
> of us assume to be a given. I would like to correct any errors and
> make sure no criticul rules are missed (such as commandment 11, You
> shall only use numeric_std).
>
> Enjoy,
> Beanut
>
<snip>
> 2. Always reset signals.
>

Not always. Only when it matters, especially in FPGAs, as otherwise
you'll have to route that signal around to places that don't really
need it. See

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_smart_reset

<snip>
> 4. All asynchronous inputs must be double synchronized to prevent
> metastability.
> http://klabs.org/richcontent/MAPLDCon00/Presentations/Session_A/A5_Erickson_S.PDF
>

As someone else has said already - be careful doing this with buses...

<snip>
> 7. If rule #6 is violated, use double synchronizer for all signals
> crossing clock domains.
>

See 4.:-)

<snip>
> 9. Implement state machines with one of the following implementations:
> a. 3 process state machine.
> One synchronous process for updating state with next_state
> One state machine process updating next_state only
> One state machine process updating outputs only
> b. 2 process state machine (preferred method)
> One synchronous process for updating state with next_state
> One state machine process updating next_state and outputs
>

I always do my state machines in a single process, it's easier to
maintain that way (I find). Never had a problem with synthesis so far...

> 10. State machines should assign outputs a hard coded value only. If
> previous values are used in signal assignment statement then a latch
> will be inferred to store that previous value.
>

If you do it all in one synch process, it's difficult to get latches :-)
Another reason for the one process approach...

All IMHO!

Cheers,
Martin

--
martin.j.thompson@xxxxxxx
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

.

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