Re: question on synthesis
- From: "Reiner Huober" <reiner@xxxxxxxxx>
- Date: 10 Oct 2005 04:24:06 -0700
> isn't the
check (in first if statement) on event attribute redundant?
Yes, but compare this (a more common pattern)
process(CLK,RESET)
begin
if (CLK'event and CLK='1') then
...
Now the CLK'event is not redundant any more. You can leave CLK'event in
your case for readability purposes.
--
Statements which can be converted to a truth table can also be
synthesized, like
Shifter:
process(clk=
begin
if clk'event and clk='1' then
for i=1 to v'high loop
v(i-1)<=v(i)
end loop;
end if;
end process;
A synchronous barrel shifter, the shift is done in parallel here.
The synthesizable subset of VHDL depends on the synthesis tool. AFAIK
there is a standard (in progress) which should contain the least common
denominator.
Hubble.
.
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