a simple addition "+" operator question

Hi,

I have the following code, which can compile without problem in
modelsim (vcom) but when i use vsim, it fails.
------------------------------------
port (
...
x : in std_logic_vector(7 downto 0);
....
);

architecture ...

signal a :std_logic_vector(10 downto 0);
begin
a <= x&"00" + x&"00";
end
-------------------------------------------
when i vcom it, it's okay, but when i run it in modelsim, it said...

# ** Fatal: (vsim-3420) Array lengths do not match. Left is (10 downto
0). Right is (0 to 11).
# Time: 0 ns Iteration: 0 Process: ...
--------------------------------------------
it's very strange, if I do a <= x&"000". It is okay.
but when i use a <= x&"00" + x&"00". it is not...
I can't understand, as i think both are equivalent....

carson

.

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