Combinational logic running over multiple clock cycles in Xilinx
- From: "Taras_96" <taras.di@xxxxxxxxx>
- Date: 20 Aug 2005 23:41:15 -0700
Hi everyone
Currently our architecture consists of 1024 really fast loops, with
each result being loaded into a register, followed by a single long
1024 bit ripple carry addition that uses the end result of the 1024
loops, and loads the addition into a register. This entire sequence is
repeated 1024 times. The addition is supposed to take place over
multiple clock cycles - the design has a state machine that allocates
a configurable number of states for this addition to take place. This
is essential because it is undesirable to be running the fast loop at
the frequency it takes to do one extremely long addition.
-----|
| | loop repeated 1024 times
| |
^ v
| REG
| |
-----.
|
|
ADDER
|
v
REG
Everything synthesises fine, and Xilinx spits out a maximum clock
frequency at the end of the synthesis. However, I suspect that the
value of the clock frequency obtained assumes that the addition
operation between the two registers should be completed in one clock
cycle (I don't see why Xilinx would assume otherwise).
My question is: is there anyway of either telling Xilinx that the
addition is supposed to take over multiple clock cycles or using Xilinx
or its results to determinine the maximum clock frequency assuming that
the addition takes place over a variable number of clock frequencies?
TIA
Taras
.
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