Re: Sequential Circuits power up Reset
- From: Jonathan Bromley <jonathan.bromley@xxxxxxxxxx>
- Date: Thu, 30 Jun 2005 17:43:20 +0100
On 30 Jun 2005 09:02:25 -0700, "john" <conphiloso@xxxxxxxxxxx> wrote:
>I am having a problem with the power up "Reset" of the 19-bit counter..
>I want it to be "0000 hex", whenever, I power up my system.
>It initializes it self to "0000hex" sometimes and sometimes it does not
>do that. I have attached the code too. Please advice!
Are you talking about behaviour of the real hardware, or simulation?
Have you simulated? Have you run synthesis? Are you sure that signal
Reset_A is indeed asserted at startup?
Did they teach you about.....
....synthesisable clocked processes?
>sec_counter<= "0000000000000000000" When Reset_A ='1' Else sec_counter
> + 1 When inc 'Event And inc= '1' And sec_stop ='0';
.... numeric comparison in the numeric_std package?
>sec_stop <= '1' When sec_counter(18)='0'and sec_counter(17)='0'and
>sec_counter(16)='0' and
>sec_counter(15)='0'and sec_counter(14)='0'and sec_counter(13)='1' and
>sec_counter(12)='0'and sec_counter(11)='0'and sec_counter(10)='1' and
>
>sec_counter(9)= '0'and sec_counter(8)= '0'and sec_counter(7)='0' and
>
>sec_counter(6) ='0'and sec_counter(5)= '1'and sec_counter(4)='0' and
>
>sec_counter(3)= '0'and sec_counter(2)= '0'and sec_counter(1)='0' and
>sec_counter(0)= '0'
>Else
> '0';
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@xxxxxxxxxx
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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