Re: Module <tb> has no port.



On Sep 27, 12:05 am, andersod2 <thechrisander...@xxxxxxxxx> wrote:
I am getting this error for this code - but can't figure out why it's
giving me that.  When I take out the declaration of uut, the error
goes away and synthesizes fine:

`timescale 1ns/1ns

module tb;

///**************************************
//* Signal/Register Declarations *
//**************************************/
reg clk;
reg reset;
reg key_0;
reg key_1;
reg key_2;
wire [07:00] led;

//      /**************************************
//      * Module Instances *
//      **************************************/

        ped uut(.clk(clk), .reset_b(reset), .sig(key_0), .pulse(led));

        // Generate Clocks
        always #10 clk = ~clk;
        initial begin
        reset = 1;
        clk = 0;
        #100 reset = 0; // De-Assert Reset after 100 ns
        end
        `include "test.v"

endmodule

Why are you trying to synthesize your testbench? It is perfectly
normal
for a testbench to have not ports. It is not normal to synthesize it.

Regards,
Gabor
.



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