Re: How to learn register and bus design

On Jul 29, 7:59 am, Very Very Log <tech.login....@xxxxxxxxx> wrote:
On Jul 29, 1:21 am, "WilliamG...@xxxxxxxxx" <williamg...@xxxxxxxxx>
wrote:





On Jul 28, 12:13 pm, Very Very Log <tech.login....@xxxxxxxxx> wrote:

On Jul 28, 9:49 pm, glen herrmannsfeldt <g...@xxxxxxxxxxxxxxxx> wrote:

Very Very Log <tech.login....@xxxxxxxxx> wrote:

I am new to designing registers and buses in Verilog.
Can someone let me know how can I learn the same?
Any good books or tutorials on the net?
I am basically looking for clear explanations on chip-select,
read-not-write, word_size, periph_ctl, periph_stat, fful,
fempty, end-of-packet, acknowledge etc.

It isn't so different from doing the same without verilog.

Well, sometimes using chips within the same family, such as
a Motorola processor and associated peripheral chips, one can
mostly ignore such timing considerations and assume that they
were designed to work together.

Pretty much there are two ways:  Design the system so conservative
(usually meaning slow) that you don't have to worry about such,
or carefully read the data sheet, much up all the parameters,
and verify that all is correct.

But do note that slow doesn't guarantee anything.  You can still
get the setup/hold times wrong no matter now slow you go.
Usually, though, for slow systems you can arrange things so that
signals change on one clock edge and are latched on the other
clock edge.  If you do that, and aren't too fast, things should
work just fine.

Start with the timing between a microprocessor and associated
ROM and RAM chips.  Then move on to more complicated systems.

-- glen

I am not sure if I understand why slow-fast should matter in the
process of learning.
I only understood your last 2 lines :)
But that does not answer my question :(
Can you name a book or some nice web tutorial where I can gain mastery
of these things?

You should clarify your request for assistance.  Are you looking for
assistance understanding registers, buses and digital design concepts
& primitive elements - or - are you looking for a Verilog/
SystemVerilog modeling textbook?

I am looking primarily for assistance understanding registers, buses
and digital design concepts & primitive elements.
If some code is there in (System)Verilog, then it would be excellent!

Any replies?
.

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