Re: generate/genvar, for loop and procdural (always/initial) block

On Nov 6, 11:01 am, Chris Briggs <ch...@xxxxxxxxx> wrote:

[snip]

. . . there are better styles for clock generators.
Personally, I still like this one from Janick Bergeron's _Writing
Testbenches_, 1st ed.:

reg clk;
initial
   forever begin
      #(period/2) clk = 1'b0;
      #(period/2) clk = 1'b1;
   end

Clock events at time 0 used to cause problems though the simulation
vendors have cleaned those up. I still like delaying the first posedge
clk though. Makes it easier to see what happens on the first clock in
waves.

-cb

That's pretty useful, thanks. No edge at time zero but X-0
edge at period/2 is still a "negedge" event consistent with
the clock's operation. I've been using the Xilinx GUI to
generate a quick starter for testbenches, but they always
fill in all the module inputs in an initial block starting
at time zero. Not a problem for rising edge only clocks
when setting the initial to 0. Of course the Xilinx stuff
has other start-up issues like their semi-hidden GSR net
that resets all their structural models (but not your
behavioral code) for the first 100 ns of the simulation.

Most of my behavioral code is written with asynchronous
reset, so what happens on the first clock isn't so important.
However I do remember having some headaches with the falling
edge event at time zero due to the initial statement. I always
thought that "initial" was for initial conditions - i.e.
everything is assumed to start from there, but of course
the LRM says otherwise, i.e. everything is X until initialized
and that X to whatever transition is an event.

Regards,
Gabor
.

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