Re: uart testbench help

On Apr 14, 6:24 pm, uraniumore...@xxxxxxxxx wrote:
On Apr 8, 3:13 am, Jonathan Bromley <jonathan.brom...@xxxxxxxxxxxxx>
wrote:





On Tue, 7 Apr 2009 22:07:27 -0700 (PDT), hairyotter wrote:
Another example of people complaining about VHDL because
they don't properly understand it. If you put the
conversion routine IN THE PORT MAP, then it doesn't
cost a delta cycle.

Jonathan, sorry, it's not easy to not take this personally.

No offence meant; it's just that I weary of all the anti-VHDL
canards that I routinely hear.

Please do notice that I did not say I did this, I said somebody else
did it

and I said "people" because I was pretty sure you didn't!

However, with all the strong typing it still is quite easy, if you're
not careful, to create unwanted phenomena, which is one of the things
that the language wanted to eliminate.

Yes, there are indeed some quite unfortunate things... fewer than
Verilog, for sure, and less pervasive, but unfortunate nonetheless.

VHDL does even have dynamically allocated structures, but writing
complex behavioural testbenches is terribly complicated (tasks ?).

Yes.  I've said many times - and will no doubt say again - that
Verilog's ability to make procedural calls into a module is the
most important thing it does to help testbench construction.
On the other hand, it is not outrageously hard to work up
a block-to-block communication scheme for your VHDL testbench
that looks suspiciously like transaction-level modeling.

Thanks
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@xxxxxxxxxxxxxxxxx://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hey guys,

I am having a real problem with this UART stuff. My problem is sending
data from the bbfifo block of Ken Chapman's Transmitter module.
Initially, I have a 32 bit register, 8 bits gets written to the fifo
at every clock cycle. I am having problems sending this 32 bit to a PC
at 9600 bps. I have verified that my reciever module is working, the
problem is my transmitter module. My clock rate is 155.52 external
clock signal on the Spartan 3AN board. Please let me know if you have
any suggestions ..

/*
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////­///////
// Company:
// Engineer:
//
// Create Date:    17:45:12 03/29/2009
// Design Name:
// Module Name:    Top_RXandTX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////­///////
module Top_RXandTX(clk, serial_out, buffer_full,serial_in, resetC,
startC, preset, reset);

//Protocol: Start, Wait for Complete, Read Numerator, Read
denominator, Reset, etc

wire [7:0] command;
reg en_16_x_baud;
reg  [9:0] baud_count;
output reg resetC;
input reset;

input clk;
//input wire reset_buffer; //reset tranfer buffer
input serial_in;
//input [31:0] numerator;
reg [31:0] glum;
//input read_buffer_rx;
wire num_avail;
reg [4:0] counter;

output preset;
output serial_out;
output buffer_full;

output reg startC;
reg startT;
reg resetCounter;
reg resetCommand;
reg sendNum;
reg sendStart;

//read an 8bit command from the reciever buffer, translate the
commands to start and reset signals

always @ (command) //test when command changes
begin
case(command) //test the command

        8'b01000001: begin  startC <=0; resetC <= 0; end  //start for one one
count session

   8'b01000010: begin  startC <=1; resetC <= 1; end       //reset for one
count session

        default   : begin  startC <=1; resetC <= 1; end   //disable counter
and enable reset signals

endcase
end

always @ (posedge clk)
begin
if(reset) //software command reset
begin

        baud_count <= 0;
        en_16_x_baud <= 0;

end
else
begin
if (baud_count == 324) //enable data rate for uart_communication to PC
                begin
                                        baud_count <= 1'b0;
                                        en_16_x_baud <= 1'b1;
                end
                else
                begin
                        baud_count <= baud_count + 1;
                        en_16_x_baud <= 1'b0;
                end
end
end

        always @ (posedge clk)
        begin
                if(startC) //reset signals
                begin
                        counter <= 0; //reset clock signa;
                        startT <= 0; //reset uart transfer
                        sendStart <= 1; //
                end
        else
        begin
                if (~startC & counter == 0 & sendStart) //start command detected,
reset counter completed, and data numerator available
                begin
                        //numerator and denominator are ready for data transfer to the
computer
                        glum <= 32'b01000100010001000100010001000100; //tranfer COMPLETION
signal
                        startT<=1; //begin transfer
                        sendStart <= 0; //start is being processed
                end
                if(~sendStart & counter == 1) //wait two clocks after, glum transfer
complete
                begin
                        startT<=0; //stop transfer after 3 clock cycles
                        sendStart <= 0; //start had been transfered
                end

                if (~startC & reset_buffer & counter == 4) //start command detected,
reset counter completed, and data numerator available
                begin
                        //numerator and denominator are ready for data transfer to the
computer
                        glum <= numerator; //tranfer numerator/denominator
                        startT<=1; //begin transfer
                        sendNum <= 1; // numerator is being processed
                end
                else if(sendNum & counter == 6 ) //wait two clocks after, glum
transfer complete
                begin
                        startT<=0; //stop transfer after 3 clock cycles
                        sendNum <= 0; //numerator has been transfered
                end
//
                counter <= counter + 1; //go to the next cycle

         end
end

//when the endount is pulsed then the the glum value gets transfered
to the computer
Top_Tx u1(clk,
                         startC,
                         serial_out,
                         buffer_full,
                         buffer_half_full,
                         en_16_x_baud,
                         glum,
                         startT
     ); //transmit glum to computer

//when a command (8-bits) is recieved the fpga decodes it, and enables
thE FPGA for one of the actions
//as soon as a 8 bit signal comes in, we reset the buffer right away
Top_Rx u2(serial_in,
                         command,
                         read_buffer_rx,
                         en_16_x_baud, clk,
                         preset,
                         buffer_full_rx,
                         buffer_half_full_rx,
                         startC); //recieve start, stop, reset instruction from the
computer

endmodule
*/

`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////­///////
// Company:
// Engineer:
//
// Create Date:    17:45:12 03/29/2009
// Design Name:
// Module Name:    Top_RXandTX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////­///////
module Top_RXandTX(clk, serial_out, buffer_full,serial_in, resetC,
startC, preset, reset, numerator, done, denominator);

//Protocol: Start, Wait for Complete, Read Numerator, Read
denominator, Reset, etc
//Notes:
//altercation: 11:32 AM baud tranfer for 50 MHz used in this module
for Behavioral simulation,
//need to change to comment option for Implementation

wire [7:0] command;
reg en_16_x_baud;
reg  [9:0] baud_count;
output reg resetC;
input reset;
input [31:0] numerator;
input [31:0] denominator;

input clk;
//input wire reset_buffer; //reset tranfer buffer
input serial_in;
//input [31:0] numerator;
reg [31:0] glum;
//input read_buffer_rx;
wire num_avail;
reg [9:0] counter;

output preset;
output serial_out;
output buffer_full;

output reg startC;
reg startT;
reg resetCounter;
reg resetCommand;
reg sendNum;
reg sendStart;
input done;
reg sendStart2;

//read an 8bit command from the reciever buffer, translate the
commands to start and reset signals

always @ (command) //test when command changes
begin
case(command) //test the command

        8'b01000001: begin  startC =0; resetC = 0; end  //start for one one
count session

   8'b01000010: begin  startC =1; resetC = 1; end       //reset for one
count session

        //default         : begin  startC =1; resetC = 1; end   //disable counter
and enable reset signals

endcase
end

always @ (posedge clk)
begin
if(reset ) //manual board reset
begin

        baud_count <= 0;
        en_16_x_baud <= 0;

end
else
begin
                if (baud_count == 1013) //enable data rate for uart_communication to
PC
                begin
                        baud_count <= 1'b0;
                        en_16_x_baud <= 1'b1;
                end
                else
                begin
                        baud_count <= baud_count + 1;
                        en_16_x_baud <= 1'b0;
                end
end
end

        always @ (posedge clk)
        begin
                if(startC) //reset signals
                begin
                        counter <= 0; //reset clock signal;
                        startT <= 0; //reset uart transfer
                        sendStart <= 1; //
                        sendStart2 <= 0; //
                end
                else
                begin

                if (~startT /*done*/  & sendStart) //start command detected, reset
counter completed, and data numerator available
                begin
                        //numerator and denominator are ready for data transfer to the
computer
                        glum <= 32'b01010101011000110110100001100101 ;
                        startT<=1; //initialize device and reset fifo buffer
                        sendStart <= 0; //start is being processed
                end
                if(startT & baud_count == ) //reset transfer at 3rd clock cycle
                begin
                        startT<=0; //stop initialization and start fifo buffer transfer
                        sendStart2 <= 1; //start numerator logic
                end

                if(~startT & sendStart2)
                begin
                        glum <= 32'b01010101010010110100000101001010;
                        startT<=1; //initialize device and reset fifo buffer
                        sendStart2 <= 0; //disable the previous
                end
                if(startT)
                begin
                        startT <= 0; //transfer transfer
                end

                counter <= counter + 1; //go to the next cycle
         end
end

//when the endount is pulsed then the the glum value gets transfered
to the computer
Top_Tx u1(clk,
                         startC,
                         serial_out,
                         buffer_full,
                         buffer_half_full,
                         en_16_x_baud,
                         glum,
                         startT
     ); //transmit glum to computer

//when a command (8-bits) is recieved the fpga decodes it, and enables
thE FPGA for one of the actions
Top_Rx u2(serial_in,
                         command,
                         1'b1,
                         en_16_x_baud, clk,
                         preset,
                         buffer_full_rx,
                         buffer_half_full_rx,
                         startC); //recieve

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always @ (posedge clk)
begin

if(startT) //initialize all registers fir one clock cycle
begin
//reset all signals
data_in<=0;
counter <= 0;
start<=1; //begin transfer
write_buffer <= 0;
data <= glum;
end
else
begin

if(start) //begin transfer
begin
if(counter == 1) //clock cycle 0
begin
data_in<=data[7:0]; //send data to port 1 byte
end

else if(counter == 2) write_buffer <= 1; //activate write to uart
port //WAIT

else if (counter == 3)
begin
data_in<=data[15:8];
end

else if (counter == 4)
begin
data_in<=data[23:16];
end

else if (counter == 5)
begin
data_in<=data[31:24];
end

else if(counter == 6)
begin
write_buffer <= 0; //stop burst writing
start <= 0; //stop transfer with uart transfer
end

counter <= counter + 1;
end

end
end

//when write is asserted, the uart_tx module writes the data_in into
the 128 bits into the buffer
//and activates the buffer_full signal
uart_tx uart_Tx(.data_in(data_in),
.write_buffer(write_buffer), //write the data_in bits into the
FIFO
.reset_buffer(startT),
.en_16_x_baud(en_16_x_baud),
.serial_out(serial_out),
.buffer_full(buffer_full),
.buffer_half_full(buffer_half_full),
.clk(clk));
//this is the reciever module. start, stop, reset bit patterns are
sent from the Rx line of the RS-232
//to this reciever module and then processed

endmodule


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