Re: Verilog and PCB layout

John Eaton <nospam@xxxxxxxx> wrote in
news:zuKdnXiACdDqjjHUnZ2dnUVZ_jCWnZ2d@xxxxxxxxxxxxxxxxxxxxxxx:

Allan Herriman wrote:


Things that didn't work quite so well the first time:

- A lot of scriping (Perl in my case) was needed to resolve the
pinouts between the board netlist and the HDL source. I was never
able to convince the board designers to use the same names for the
schematic symbols that I used on the HDL ports, forcing a pinout file
(e.g. UCF for Xilinx) to be used to map the pin numbers to names.

More recently (in the last half a decade or so) I've changed my
process such that I take the port names in my HDL source from the pin
or net names on the schematic. I use a (Perl) script to generate
most my top level HDL module directly from the schematic netlist.
My project schedules usually work out such the the board guy has
finished the schematic before I want to write the top level HDL
module.

Allan,

How does your team create the schematic symbol for your parts?
Do you
have a librarian that takes your data *** and builds the part? If
they are simply taking shortcuts and renaming your pin_names at will
then you should put a stop to that. Their symbol pin_names should
exactly match what is in your data ***.


Sometimes the symbol pin_names are created before the data *** is
created. I find it easier to make the data *** (and the HDL source)
match the symbol in that case.


- A large number of connections are related to things that you don't
want to simulate at all, e.g. power supply connections. You will
need to be able to identify these in your scripts.


If you don't test it then it won't work. If the board designer only
connects 9 out of 10 grounds to your part then your simulation should
catch it.

[ I should clarify that my statement about not simulating power supplies
was in relation to digital simulations, specifically verilog ones. I
actually spend a lot of time designing, simulating and reviewing power
supplies and their connections, but not in verilog. ]

Interestingly, I don't recall ever finding a power supply or ground
connection fault in simulation. I guess it comes down to whether you
design something so that it works, or whether you believe something needs
to be tested to work.

If it's a PCB, then I'm in the "design & review" camp. An hour or two
eyeballing the power supply connections on the schematic provides a
balance between effort and risk. I don't think I've ever made a power
supply connection error. (YMMV, of course. If you find that your
designers can't connect power supplies correctly, then simulation may
help.)

[This is getting a bit OT for c.l.v] I spend far more time in the PCB
editor verifying the *quality* of the power supply and decoupling than
just about anything else in the board design verification process.
We don't use automatic model extraction for the power supplies here, so
all this is done manually :(

Regards,
Allan
.