Re: Is Function/Task synthesizable?



On Jan 3, 4:25 pm, Ryan <Ryan.Warner...@xxxxxxxxx> wrote:
On Jan 3, 3:54 am, humann <hongqing...@xxxxxxxxx> wrote:



The concept of "code reuse" in software is function.

Every software guy knows that calling a function in C is
1. push parameters in stack
2. point pc counter to the begin address of the function

what happens in Verilog if I call a function, both in simulation or in
a chip?

1. Is function/task in Verilog synthesizable? or It works just in
simulation.
2. If I call a function several times, what does it means?
2.1 I use a hardware several time
2.2 I duplicate hardware in Chip.
3. How can I use a hardware in a "time-sharing" fashion? (for
Example: to save power or save area)

Whether it is synthesizable or not, largely depends on how you use
it. Since you obviously know software I assume you have books on the
subject. Since you are trying to learn about hardware synthesis, I
recommend the same for this subject. A classic is HDL CHIP DESIGN by
Doublas J. Smith.

When software types first dive into synthesis they often find they
have a hard time meeting timing.
What does "meeting timing" means? timing analyse?

That is because they are only thinking logically and not physically
This description is to the point. It is the most difficult part for
me
to learn verilog.

Ultimately you are doing
circuit design, and you need to know what circuit will be generated by
the code you write.
I will try to "thinking more physically".
There are any tools which I can see my code as circuits intuitively?
Synopsys Design Compiler? There are any good tutorials for it with
example code?

I like this book because it approaches HDL from a
circuit design perspective instead of a language perspective. It give
examples of most of the basic building block circuits you would want
to use, and examples in both verilog and vhdl that will generate said
circuit.
Thank you for your tip.
.



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