a question about fsm confusing me for a long time

I am designing a state machine that will be fit into a FPGA.
The state machine have 9 states.Every state except idle state needs to
wait certain number of clockes (
for example, 80 clockes here,or maybe longer ,even 1000 clockes ). I
use counter in every state to hold current state.My question is I need
to load the counter in every state and counting,how can I seperate
the counter from the state ?When counting to 1000 clocks,the system
frequence is low,how to resolve it?
my code:
always @ (posedge clock)
case(cs)
idle: cs<=s0;
s0: begin
if(count==79) begin
count<=0;
cs<=s1;
end
else
count<=count+1'b1;
end
s1:.......

.

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