Re: How to "import" an interface into a module w/o `include?
- From: Jonathan Bromley <jonathan.bromley@xxxxxxxxxxxxx>
- Date: Tue, 11 Sep 2007 22:36:24 +0100
On Tue, 11 Sep 2007 20:01:28 -0000,
mrfirmware <mrfirmware@xxxxxxxxx> wrote:
[...]<mrfirmw...@xxxxxxxxx> wrote:
I'd like to have a file with an interface in it and then "import" it
into my top level testbench.sv file. Something like this:
// File: my_if.sv
interface my_if;
...
endinterface : my_if
---
// File testbench.sv
import my_if::*;
module testbench;
my_if if0;
...
endmodule : testbench
There's something very basic I'm missing here, I realize that.
[ModelSim/Questa] (v6.3b). I do compile different sources into different
libs but not one file per lib. Must I?
No, certainly not. In fact, many people work with just one
single library for the entire project; that's OK too.
I've got my RTL in lib nz_rtl,
my testbench and top level .sv files in lib nz_top, and my packages in
nz_pkg.
Do you mean the source files are in those directories, or
do you mean that you have used 'vlog' to compile your source files
into ModelSim libraries of those names? If these are simply
the names of directories that contain your source code, then
they are not "libraries" at all and your use of the -L option
is misplaced.
I put my sole a typedef package file and the interface file
into nz_pkg and then tell vlog about all the library dirs via -L
nz_rtl -L nz_pkg, etc. However, vlog just complains that 'my_if' is an
undefined variable (which isn't too surprising as I don't know how it
could possibly know it's an interface).
Ahah... Do you *really* mean that it's *vlog* complaining (not vsim) ?
If so, it's simple... You don't want the -L option at that stage,
unless you're using packages. You need the -L option to 'vsim'
to tell it the names of all the libraries into which you've compiled
your various SystemVerilog modules and interfaces.
Just as a for-instance...
Suppose you have this file tree:
project_home/
project_home/sim/ ---- working dir for the simulator
project_home/sources/ ---- dir to hold all source code
project_home/sources/nz_pkg/
project_home/sources/nz_pkg/your_interface.sv
project_home/sources/nz_pkg/your_package.sv
project_home/sources/nz_rtl/
project_home/sources/nz_rtl/your_module1.sv
project_home/sources/nz_rtl/your_module2.sv
project_home/sources/nz_top/
project_home/sources/nz_top/your_design_top.sv
project_home/sources/nz_top/your_testbench.sv
File "your_package.sv" contains a package:
package your_package;
...
endpackage : your_package
Most of the other files import it; for example,
file "your_interface.sv" might look like this:
import your_package::*;
interface your_interface;
...
endinterface
And the instance hierarchy will be
your_testbench
|
|__ your_design_top
|
|__ your_module1
|
|__ your_interface
|
|__ your_module2
My compile/load script for ModelSim might look
something like this:
cd project_home/sim
# make a bunch of libraries - only needed on first run of
# the script, will give harmless warnings on later runs
vlib pkg_lib; # make a ModelSim lib for the packages
vlib rtl_lib; # and another for the RTL design
vlib tb_lib; # and a third for the testbench
# compile package first, into pkg_lib
vlog -work pkg_lib ../sources/nz_pkg/your_package.sv
# now compile all the other code, in any order;
# make pkg_lib visible to each compile so they can
# import the package as needed; put design modules
# into "rtl_lib" and testbench modules into "tb_lib"
vlog -work rtl_lib -L pkg_lib ../sources/nz_pkg/your_interface.sv
vlog -work rtl_lib -L pkg_lib ../sources/nz_rtl/*.sv
vlog -work rtl_lib -L pkg_lib ../sources/nz_top/your_design_top.sv
vlog -work tb_lib -L pkg_lib ../sources/nz_top/your_testbench.sv
# OK, now everything compiled, load it into ModelSim
# making sure that the simulator looks in the right libs
vsim -novopt -L pkg_lib -L rtl_lib tb_lib.your_testbench
Natch, you may want to add a bunch of other options on some
of these commands. The point I'm really trying to get across
is that a directory full of source code is absolutely NOT the
same as a ModelSim library. (Please, please don't get me
started about Verilog configurations and "libraries", the
Verilog library mapping file [as opposed to ModelSim's
library mapping] and the `uselib directive. That would
take too long, and it's not at all clear my blood pressure
would cope.)
Hope this makes some sense.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
.
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