Re: Frequency synthesis
- From: gabor <gabor@xxxxxxxxxxx>
- Date: Wed, 11 Jul 2007 05:54:34 -0700
On Jul 10, 6:37 pm, "devices" <me@home> wrote:
"gabor" <g...@xxxxxxxxxxx> wrote in message
news:1184076237.110126.77030@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
I seem to remember a number of threads about generating a fractional
frequency
for such things as baud rate. One approach is to use DDS, usually
with a
power of two divisor. For large numbers of bits you can get good
frequency
resolution, but you always end up with cycle jitter when your output
frequency
is not a power of two division of the input frequency. Also any
fraction not
reduceable to n over a power of two will not come out exact.
This code uses DDS with a variable divisor to allow jitter free output
for integer division of the input frequency, and exact fractional
frequencies with the usual induced cycle jitter for other
frequencies. The output is relatively square and must be less than
or equal to 1/2 the input frequency. If you want to use the code
to generate a clock enable instead of a square wave, the
output rate can go up to the input frequency as noted below.
I find this very easy to implement and also very compact:
http://www.fpga4fun.com/SerialInterface2.html
Yes, this is the traditional DDS using a power of two
(in the non-paramterized case 1024) as the divisor.
The good explanation makes it easy to understand and to
customize. The only two parameters needed are the
accumulator's width (related to the multiplier) and the divider.
The use of a spreadsheet is essential in order to find an optimal
value. I try some width values - Wi - and choose the one that,
keeping the wanted ratio, asks for a divider that is
closer to an integer number. Suppose
W1 gives D1 = D(W1) = 34.5
and
W2 gives D2 = D(W2) = 34.1,
i choose W2 / D2
Another interesting point with baud rate dividers is the standard
use of the 16x clock for receiving. This is a holdover to the
original UART chips that did not have internal baud rate counters.
Usually in an FPGA you have a clock that has a high enough frequency
that a simple integer division provides enough accuracy for a 1x
baud rate. In the case of 115200 baud for example, you can be
within 0.5% of the actual rate given an integer divide of any
frequency larger than 23 MHz, a pretty slow clock for modern
FPGA's. Multiply that by 16 and then you get into trouble with
the simple divider.
For my UARTs I generally use a simple integer divide to generate
the receive clock, there the divider gives a 1x clock output. At
the falling edge of the start bit I reset the counter to 1/2 of
the divisor. This provides a center-bit sampling pulse when the
count carries out. This method effectively combines the baud
generation and center sampling logic. Of course you'll need a
separate non-resetting counter to generate your transmit clock.
Cheers,
Gabor
.
- References:
- Frequency synthesis
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